
12
6/2001
REV. PrB
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
PRELIMINARY TECHNICAL DATA
SLAVE MODE
This section describes the Slave Mode memory configura-
tion of the Modem Processors.
INTERNAL MEMORY DMA PORT (IDMA PORT)
The IDMA Port provides an efficient way for a host system
and the ADSP-21mod980N to communicate. The port is
used to access the on-chip program memory and data mem-
ory of each modem processor with only one processor cycle
per word overhead. The IDMA port cannot be used, how-
Figure 7. Programmable Flag
1
& Composite Select Control Register
1
Since they are multiplexed within the ADSP-21mod980N, PF[2:0] should be configured as an output for only one processor at a time. Bit [3] of DM
(0x3FE6) must also be 0 to ensure that PF[3] is never an output.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
DM(0x3FE6)
PFTYPE
0 = Input
1 = Output
CMSSEL
0 = Disable CMS
1 = Enable CMS
(where bit: 11-IOM, 10-BM, 9-DM, 8-PM)
BMWAIT
Figure 8. System Control Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
SPORT1 Enable
0 = Disable
1 = Enable
PWAIT
Program Memory
Wait States
SPORT1 Configure
0 = FI, FO, IRQ0, IRQ1, SCLK
1= SPORT1
Disable BMS
0 = Enable BMS
1 = Disable BMS, except when
memory strobes are three-stated
SPORT0 Enable
0 = Disable
1 = Enable
DM(0x3FFF)
RESERVED
SET TO 0
Reserved Set
To 0
Table 6. ADSP-21mod980N Mode of Operation
MODE C
MODE B
MODE A
Booting Method
1
0
1
IDMA feature is used to load internal memory as desired. Program execution is held off until internal
program memory location 0x0000 is written to. Chip is configured in Slave Mode.
1
IACK requires
external pulldown.
2
1
Considered standard operating settings. These configurations simplify your design and improve memory management.
2
IDMA timing details and the correct usage of IACK are described in the
ADSP-2100 Family User’s Manual
.