- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374037 > ADSP-21MOD980N (Analog Devices, Inc.) MultiPort Internet Gateway Processor PDF資料下載
參數(shù)資料
| 型號： | ADSP-21MOD980N |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | MultiPort Internet Gateway Processor |
| 中文描述： | 通寶互聯(lián)網(wǎng)網(wǎng)關(guān)處理器 |
| 文件頁數(shù)： | 5/42頁 |
| 文件大小： | 566K |
| 代理商： | ADSP-21MOD980N |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
5
REV. PrB
6/2001
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
PRELIMINARY TECHNICAL DATA
All eight modem processors have identical functions and
have equal status. Each of the modem processors is con-
nected to a common IDMA bus and each modem processor
is configured to operate in the same mode (see the slave
mode and the memory mode descriptions in
“
Memory
Architecture
”
on page 10
). The slave mode is considered to
be the only mode of operation in the ADSP-21mod980N
modem pool.
SERIAL PORTS
The ADSP-21mod980N has a multichannel serial port
(SPORT) connected to each internal digital modem pro-
cessor for serial communications.
The following is a brief list of ADSP-21mod980N SPORT
features. For additional information on the internal Serial
Ports, refer to the ADSP-2100 Family User
’
s Manual. Each
SPORT:
is bidirectional and has a separate, double-buffered
transmit and receive section.
can use an external serial clock or generate its own
serial clock internally.
has independent framing for the receive and transmit
sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally
generated. Frame sync signals are active high or
inverted, with either of two pulse widths and timings.
supports serial data word lengths from 3 to 16 bits and
provides optional A-law and μ-law companding accord-
ing to CCITT recommendation G.711.
receive and transmit sections can generate unique
interrupts on completing a data word transfer.
can receive and transmit an entire circular buffer of
data with one overhead cycle per data word. An inter-
rupt is generated after a data buffer transfer.
A multichannel interface selectively receives and transmits a
24 or 32 word, time-division multiplexed, serial bitstream.
PIN DESCRIPTIONS
The ADSP-21mod980N is available in a 352-lead PBGA
package. In order to maintain maximum functionality and
reduce package size and pin count, some serial port, pro-
grammable flag, interrupt and external bus pins have dual,
multiplexed functionality. The external bus pins are config-
ured during RESET only, while serial port pins are software
configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins.
Table on page 6
lists the pin names and their functions. In
cases where pin functionality is reconfigurable, the default
state is shown in plain text; alternate functionality is shown
in italics.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21MOD980N-000 | CAP 27PF 100V 10% X7R AXIAL BULK M-MIL-PRF-39014 |
| ADSP-21MSP58BST-104 | DSP Microcomputers |
| ADSP-BF531 | Blackfin Embedded Processor |
| ADSP-BF531SBBC400 | Metal Connector Backshell |
| ADSP-BF531SBBZ400 | Blackfin Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21MSP50ABG-52 | 制造商:Analog Devices 功能描述: |
| adsp-21msp50akg-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| ADSP-21MSP50BG-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-21MSP50KG-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-21MSP52-520010 | 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。