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參數資料
| 型號： | ADSP-21MOD980N |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | MultiPort Internet Gateway Processor |
| 中文描述： | 通寶互聯網網關處理器 |
| 文件頁數： | 8/42頁 |
| 文件大小： | 566K |
| 代理商： | ADSP-21MOD980N |
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8
6/2001
REV. PrB
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
PRELIMINARY TECHNICAL DATA
of power-down features. Refer to the ADSP-2100 Family
User
’
s Manual,
“
System Interface
”
chapter, for detailed
information about the power-down feature.
Quick recovery from power down. The modem pool
begins executing instructions in as few as 200 CLKIN
cycles.
Support for an externally generated TTL or CMOS
processor clock. The external clock can continue run-
ning during power down without affecting the lowest
power rating and 200 CLKIN cycle recovery.
Power down is initiated by the software power-down
force bit. Interrupt support allows an unlimited num-
ber of instructions to be executed before optionally
powering down.
Context clear/save control allows the modem pool to
continue where it left off or start with a clean context
when leaving the power down state.
The RESET pin also can be used to terminate power
down.
IDLE
When the ADSP-21mod980N is in the Idle Mode, the
modem pool waits indefinitely in a low power state until an
interrupt occurs. When an unmasked interrupt occurs, it is
serviced; execution then continues with the instruction fol-
lowing the IDLE instruction. In Idle mode IDMA, BDMA
and autobuffer cycle steals still occur.
SLOW IDLE
The IDLE instruction is enhanced on the
ADSP-21mod980N to let the modem pool
’
s internal clock
signal be slowed, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the
normal clock rate, is specified by a selectable divisor given
in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the
modem pool fully functional, but operating at the slower
clock rate. While it is in this state, the modem pool
’
s other
internal clock signals, such as SCLK, CLKOUT, and timer
clock, are reduced by the same ratio. The default form of
the instruction, when no clock divisor is given, is the stan-
dard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows
down the modem pool
’
s internal clock and thus its response
time to incoming interrupts. The one-cycle response time
of the standard idle state is increased by n, the clock divisor.
When an enabled interrupt is received, the
ADSP-21mod980N will remain in the idle state for up to a
maximum of n modem pool cycles (n = 16, 32, 64, or 128)
before resuming normal operation.
When the IDLE (n) instruction is used in systems that have
an externally generated serial clock (SCLK), the serial clock
rate may be faster than the modem pool
’
s reduced internal
clock rate. Under these conditions, interrupts must not be
generated at a faster rate than can be serviced, due to the
additional time the modem pool takes to come out of the
idle state (a maximum of n cycles).
SYSTEM CONFIGURATION
Figure on page 9
shows the hardware interfaces for a typi-
cal multichannel modem configuration with the
ADSP-21mod980N. Other system design considerations
such as host processing requirements, electrical loading,
and overall bus timing must all be met. A line interface can
be used to connect the multichannel subscriber or client
data stream to the multichannel serial port of the
ADSP-21mod980N. The IDMA port of the
ADSP-21mod980N is used to give a host processor full
access to the internal memory of the ADSP-21mod980N.
This lets the host dynamically configure the
ADSP-21mod980N by loading code and data into its inter-
nal memory. This configuration also lets the host access
server data directly from the ADSP-21mod980N
’
s internal
memory. In this configuration, the Modem Processors
should be put into host memory mode where Mode C = 1,
Mode B = 0, and Mode A = 1.
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