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參數資料
| 型號： | ADSP-21MOD980N |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | MultiPort Internet Gateway Processor |
| 中文描述： | 通寶互聯網網關處理器 |
| 文件頁數： | 7/42頁 |
| 文件大小： | 566K |
| 代理商： | ADSP-21MOD980N |
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7
REV. PrB
6/2001
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
PRELIMINARY TECHNICAL DATA
INTERRUPTS
The interrupt controller allows each modem processor in
the modem pool to respond individually to eleven possible
interrupts and RESET with minimum overhead. The
ADSP-21mod980N provides four dedicated external inter-
rupt input pins, IRQ2, IRQL1, IRQL0, and IRQE (shared
with the PF[7:4] pins) for each modem processor. The
ADSP-21mod980N also supports internal interrupts from
the timer, the byte DMA port, the serial port, software, and
the power-down control circuit. The interrupt levels are
internally prioritized and individually maskable (except
power down and RESET). The IRQ2, IRQ1, and IRQ0
input pins can be programmed to be either level- or
edge-sensitive. IRQL0 and IRQL1 are level-sensitive and
IRQE is edge sensitive. The priorities and vector addresses
of all interrupts are shown in
Table on page 7
. When the
modem pool is reset, interrupt servicing is disabled.
LOW POWER OPERATION
The ADSP-21mod980N has three low power modes that
significantly reduce the power dissipation when the device
operates under standby conditions. These modes are:
Power Down
Idle
Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
POWER DOWN
The ADSP-21mod980N modem pool has a low power fea-
ture that lets the modem pool enter a very low power
dormant state through software control. Here is a brief list
Table 2. Host Pins (Mode C = 1) Modem Processors 1-8
Pin Name
# of
Pins
Input/
Output
Function
IAD[15:0]
32
1
1
There are two distinct IAD buses. One addresses DSPs 1-4 and the other
communicates with DSPs 5-8. See Figure 2 for details.
I/O
IDMA Port
Address/Data Bus
A0
1
O
Address Pin for Exter-
nal I/O, Program,
Data, or Byte access
D[23:8]
16
I/O
Data I/O Pins for Pro-
gram, Data Byte and
I/O spaces
IWR
2
1
I
IDMA Write Enable
IRD
2
1
I
IDMA Read Enable
IAL
2
1
I
IDMA Address Latch
Pin
IS
8
I
IDMA Selects
IACK
2
1
O
IDMA Port Acknowl-
edge Configurable in
Mode D; Open Drain
Table 3. Interrupt Priority and Interrupt Vector
Addresses
Source Of Interrupt
Interrupt Vector Address
(Hex)
RESET (or Power-Up
with PUCR = 1)
0x0000 (Highest Priority)
Power Down
(Nonmaskable)
0x002C
IRQ2
0x0004
IRQL1
0x0008
IRQL0
0x000C
SPORT0 Transmit
0x0010
SPORT0 Receive
0x0014
IRQE
0x0018
BDMA Interrupt
0x001C
SPORT1 Transmit or
IRQ1
0x0020
SPORT1 Receive or
IRQ0
0x0024
Timer
0x0028 (Lowest Priority)
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