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| 型號(hào)： | ADSP-21MOD980N |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | MultiPort Internet Gateway Processor |
| 中文描述： | 通寶互聯(lián)網(wǎng)網(wǎng)關(guān)處理器 |
| 文件頁(yè)數(shù)： | 4/42頁(yè) |
| 文件大小： | 566K |
| 代理商： | ADSP-21MOD980N |
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4
6/2001
REV. PrB
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
PRELIMINARY TECHNICAL DATA
ARCHITECTURE OVERVIEW
Figure 2 on page 4 is a functional block diagram of the
ADSP-21mod980N. It contains eight independent digital
signal processors.
Every modem processor has:
A DSP core
256K bytes of RAM
Two serial ports
An IDMA host.
The signals of each modem processor are accessed through
the external pins of the ADSP-21mod980N. Some signals
are bussed with the signals of the other processors and are
accessed through a single external pin. Other signals remain
separate and they are accessed through separate external
pins for each processor.
The arrangement of the eight modem processors in the
ADSP-21mod980N makes one basic configuration possi-
ble: a
slave
configuration. In this configuration, the data
pins of all eight processors connect to a single bus structure.
Figure 2. ADSP-21mod980N Functional Block Diagram
IAD<15:0>, IDMA CNTL
PF<0:2>/MODE A:C
20
3
2188N
2188N
2188N
2188N
2188N
17
2188N
4
4
8
4
2188N
2188N
20
SPORT1
SPORT0A
CLKIN
EMULATOR
SUBTOTAL = 177 SIGNAL BALLS
SIGNALS ROUTED TO EACH RESPECTIVE DIE
8
BG <8:1>
8
BR <8:1>
EE <8:1>
8
IS <8:1>
8
RESET <8:1>
8
CLKOUT <8:1>
8
TFS0 <8:1>
8
DT1 <8:1>
8
INTERRUPTS <8:1>
32
22
VDDINT
44
VDDEXT
SUBTOTAL = 175 POWER BALLS
TOTAL = 352 BALLS
109
GND
DATA<23:8>, A<0>
IAD <15:0>,
IDMA CNTL
SPORT0B
IDMA CNTL = IAL, IRD, IWR, IACK
INTERRUPTS = IRQE (PF4), IRQL0(PF5), IRQL1(PF6), IRQ2(PF7)
EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK
ELOUT, ERESET
SPORT0A, SPORT 0B
= RFS0, DR0, DT0, SCKL0
SPORT1 = RFS1, TFS1, DR1, SCKL1
NOTE:
1. PWD AND PF3/MODE D ARE TIED HIGH
DSP 1
DSP 2
DSP 3
DSP 4
DSP 5
DSP 6
DSP 7
DSP 8
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