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參數資料
| 型號： | EP2AGX125EF29C5N |
| 廠商： | Altera |
| 文件頁數： | 57/90頁 |
| 文件大小： | 0K |
| 描述： | IC ARRIA II GX FPGA 125K 780FBGA |
| 產品培訓模塊： | Arria II GX FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 4 |
| 系列： | Arria II GX |
| LAB/CLB數： | 4964 |
| 邏輯元件/單元數： | 118143 |
| RAM 位總計： | 8315904 |
| 輸入/輸出數： | 372 |
| 電源電壓： | 0.87 V ~ 0.93 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 780-BBGA |
| 供應商設備封裝： | 780-FBGA（29x29） |
| 其它名稱： | 544-2645 |
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Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
OBSAI Receiver Jitter Tolerance (15)
Deterministic jitter tolerance at
768 Mbps, 1536 Mbps, and
3072 Mbps
Pattern = CJPAT
> 0.37
UI
Combined deterministic and
random jitter tolerance at 768
Mbps, 1536 Mbps, and 3072
Mbps
Pattern = CJPAT
> 0.55
UI
Sinusoidal jitter tolerance at 768
Mbps
Jitter frequency = 5.4 KHz
Pattern = CJPAT
> 8.5
UI
Jitter frequency = 460 MHz to 20
MHz
Pattern = CJPAT
> 0.1
UI
Sinusoidal jitter tolerance at
1536 Mbps
Jitter frequency = 10.9 KHz
Pattern = CJPAT
> 8.5
UI
Jitter frequency = 921.6 MHz to 20
MHz
Pattern = CJPAT
> 0.1
UI
Sinusoidal jitter tolerance at
3072 Mbps
Jitter frequency = 21.8 KHz
Pattern = CJPAT
> 8.5
UI
Jitter frequency = 1843.2 MHz to
20 MHz
Pattern = CJPAT
> 0.1
UI
Notes to Table 1–41:
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The jitter numbers are valid for the stated conditions only.
(3) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(4) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(5) The Fibre Channel transmitter jitter generation numbers are compliant to the specification at the
T inter operability point.
(6) The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at the
R interpretability point.
(7) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(8) The jitter numbers for PCIe are compliant to the PCIe Base Specification 2.0.
(9) Arria II GZ PCIe receivers are compliant to this specification provided the VTX-CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50 mV.
(10) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3.
(11) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(12) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(13) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification.
(14) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(15) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 7 of 7)
Symbol/
Description
Conditions
–C3 and –I3
–C4 and –I4
Unit
Min
Typ
Max
Min
Typ
Max
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EP2AGX125EF29C5NES | 制造商:Altera Corporation 功能描述:FPGA Arria |
| EP2AGX125EF29C6 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 4964 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2AGX125EF29C6ES | 制造商:Altera Corporation 功能描述:FPGA Arria |
| EP2AGX125EF29C6N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 4964 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2AGX125EF29C6NES | 制造商:Altera Corporation 功能描述:FPGA Arria |
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