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參數資料
| 型號： | EP2AGX125EF29C5N |
| 廠商： | Altera |
| 文件頁數： | 7/90頁 |
| 文件大小： | 0K |
| 描述： | IC ARRIA II GX FPGA 125K 780FBGA |
| 產品培訓模塊： | Arria II GX FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 4 |
| 系列： | Arria II GX |
| LAB/CLB數： | 4964 |
| 邏輯元件/單元數： | 118143 |
| RAM 位總計： | 8315904 |
| 輸入/輸出數： | 372 |
| 電源電壓： | 0.87 V ~ 0.93 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 780-BBGA |
| 供應商設備封裝： | 780-FBGA（29x29） |
| 其它名稱： | 544-2645 |
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Chapter 1: Device Datasheet for Arria II Devices
1–7
Electrical Characteristics
December 2013
Altera Corporation
DC Characteristics
This section lists the supply current, I/O pin leakage current, on-chip termination
(OCT) accuracy and variation, input pin capacitance, internal weak pull-up and
pull-down resistance, hot socketing, and Schmitt trigger input specifications.
Supply Current
Standby current is the current the device draws after the device is configured with no
inputs or outputs toggling and no activity in the device. Because these currents vary
largely with the resources used, use the Microsoft Excel-based Early Power Estimator
(EPE) to get supply current estimates for your design.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter.
VCCL_GXBLn
Transceiver clock power (left side)
—
1.05
1.1
1.15
V
VCCL_GXBRn
Transceiver clock power (right side)
—
1.05
1.1
1.15
V
VCCH_GXBLn
Transmitter output buffer power (left side)
—
1.33/1.425
1.4/1.5 (5)
1.575
V
VCCH_GXBRn
Transmitter output buffer power (right side)
—
TJ
Operating junction temperature
Commercial
0
—
85
°C
Industrial
–40
—
100
°C
tRAMP
Power supply ramp time
Normal POR
(PORSEL=0)
0.05
—
100
ms
Fast POR
(PORSEL=1)
0.05
—
4
ms
Notes to Table 1–6:
(1) Altera recommends a 3.0-V nominal battery voltage when connecting VCCBAT to a battery for volatile key backup. If you do not use the volatile
security key, you may connect the VCCBAT to either GND or a 3.0-V power supply.
(2) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V.
(3) n = 0, 1, or 2.
(4) VCCA_L/R must be connected to a 3.0-V supply if the clock multiplier unit (CMU) phase-locked loop (PLL), receiver clock data recovery (CDR), or
both, are configured at a base data rate > 4.25 Gbps. For data rates up to 4.25 Gbps, you can connect VCCA_L/R to either 3.0 V or 2.5 V.
(5) VCCH_GXBL/R must be connected to a 1.4-V supply if the transmitter channel data rate is > 6.5 Gbps. For data rates up to 6.5 Gbps, you can connect
VCCH_GXBL/R to either 1.4 V or 1.5 V.
(6) Transceiver power supplies do not have power-on-reset (POR) circuitry. After initial power-up, violating the transceiver power supply operating
conditions could lead to unpredictable link behavior.
Table 1–6. Recommended Operating Conditions for Arria II GZ Devices (Note 6) (Part 2 of 2)
Symbol
Description
Condition
Minimum
Typical
Maximum
Unit
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EP2AGX125EF29C5NES | 制造商:Altera Corporation 功能描述:FPGA Arria |
| EP2AGX125EF29C6 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 4964 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2AGX125EF29C6ES | 制造商:Altera Corporation 功能描述:FPGA Arria |
| EP2AGX125EF29C6N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 4964 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2AGX125EF29C6NES | 制造商:Altera Corporation 功能描述:FPGA Arria |
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