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參數資料
| 型號： | GS9090-CNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI |
| 中文描述： | GS9090 GenLINX - R的第三270Mb / s的SDI和DVB解串器，意大利航天局 |
| 文件頁數： | 23/70頁 |
| 文件大小： | 696K |
| 代理商： | GS9090-CNE3 |
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GS9090 Data Sheet
28201 - 1
July 2005
23 of 70
Figure 3-2: Lock Detection Process
The lock detection algorithm first determines if a valid serial digital input signal has
been presented to the device by sampling the internal carrier_detect signal. When
the serial data input is considered invalid the LOCKED pin will be set LOW, and all
device outputs will be forced LOW, except PCLK. The PCLK output frequency will
be 27MHz +/- 7.5% over the temperature range of -20
o
C to +85
o
C.
If a valid serial digital input signal has been detected, and the device is in Auto
mode, the lock algorithm will attempt to detect the presence of either SMPTE TRS
words or DVB-ASI sync words. Assuming that a valid 270Mb/s SMPTE or DVB-ASI
signal has been applied to the device, the LOCKED pin will be set HIGH and the
synchronous and asynchronous lock times will be as listed in the
AC Electrical
Characteristics
table.
In Manual mode, the application layer must set the SMPTE_BYPASS and
DVB_ASI pins appropriately so that the lock detect block will search for either
SMPTE TRS or DVB-ASI sync words. Synchronous and asynchronous lock times
are also listed in the
AC Electrical Characteristics
table.
Power Up
or RESET
NO
YES
(Device in
Manual Mode)
Valid Serial
Digital Input
Internal reclocker
locked
Device in Auto Mode
SMPTE TRS or
DVB-ASI sync words
detected
Application layer must set SMPTE_BYPASS
and DVB_ASI pins to support different
functionalities.
sets SMPTE_BYPASS
and DVB_ASI pins LOW
Device
Device
sets LOCKED
pin LOW
Device sets
LOCKED pin HIGH
Device sets SMPTE_BYPASS
and DVB_ASI status pins
(Section 3.5.2)
Device outputs accurate
27MHz clock on PCLK pin
Device
outputs 27MHz +/- 7.5%
clock on PCLK pin
Device
sets all other
output pins LOW
(Input data invalid)
YES
NO
NO
NO
YES
YES
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