- 您現在的位置：買賣IC網 > PDF目錄385345 > GS9090-CNE3 (Gennum Corporation) GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI PDF資料下載
參數資料
| 型號： | GS9090-CNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI |
| 中文描述： | GS9090 GenLINX - R的第三270Mb / s的SDI和DVB解串器，意大利航天局 |
| 文件頁數： | 44/70頁 |
| 文件大小： | 696K |
| 代理商： | GS9090-CNE3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁
GS9090 Data Sheet
28201 - 1
July 2005
44 of 70
3.9.8.1 Illegal Code Remapping
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the
GS9090 will remap all codes within the active picture between the values 3FCh and
3FFh to 3FBh. All codes within the active picture area between the values 00h and
03h will be re-mapped to 04h.
In addition, 8-bit TRS and ancillary data preambles will be remapped to 10-bit
values if this feature is enabled.
Table 3-14: Host Interface Description for Internal Processing Disable Register
Register Name
Bit
Name
Description
R/W
Default
IOPROC_DISABLE
Address: 00h
15-10
–
Not Used
–
–
9
ANC_PKT_EXT
Ancillary Packet Extraction. When the FIFO is
configured for Ancillary Data Extraction mode, the
application layer must set this bit HIGH to begin
extraction.
NOTE: Setting ANC_PKT_EXT LOW will not
automatically disable ancillary data extraction (see
Ancillary Data Extraction and Reading on page 51
).
R/W
0
8-7
FIFO_MODE[1:0]
FIFO Mode: These bits control which mode the internal
FIFO is operating in (see
Table 3-15
)
R/W
0
6
H_CONFIG
Horizontal sync timing output configuration. Set LOW
for active line blanking timing. Set HIGH for H blanking
based on the H bit setting of the TRS word. See
Figure 3-3
in
HVF Timing Signal Generation on
page 28.
R/W
0
5-4
Not Used.
3
ILLEGAL_REMAP
Illegal Code re-mapping. Correction of illegal code
words within the active picture. Set HIGH to disable.
The IOPROC_EN pin must be set HIGH.
R/W
0
2
EDH_CRC_INS
Error Detection & Handling (EDH) Cyclical Redundancy
Check (CRC) error correction insertion. Set HIGH to
disable. The IOPROC_EN pin must be set HIGH.
R/W
0
1
ANC_CSUM_INS
Ancillary Data Checksum insertion. Set HIGH to
disable. The IOPROC_EN pin must be set HIGH.
R/W
0
0
TRS_INS
Timing Reference Signal Insertion. The device will
correct TRS based errors when set LOW (see
TRS
Error Correction on page 45
). The IOPROC_EN pin
must also be HIGH.
Set this bit HIGH to disable.
R/W
0
相關PDF資料 |
PDF描述 |
|---|---|
| GS9092A | GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092ACNE3 | GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092 | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092-CNE3 | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GSC9620 | P-CHANNEL ENHANCEMENT MODE POWER MOSFET |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS9091B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX II 270Mb/s Deserializer for SDI and DVB-ASI |
| GS9091BCBE3 | 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 功能:解串器 數據速率:2.5Gbps 輸入類型:串行 輸出類型:并聯 輸入數:- 輸出數:24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應商設備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| GS9092 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092A_10 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX III 270Mb/s Serializer for SDI and DVB-ASI |
發布緊急采購，3分鐘左右您將得到回復。