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參數資料
| 型號： | GS9090-CNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI |
| 中文描述： | GS9090 GenLINX - R的第三270Mb / s的SDI和DVB解串器，意大利航天局 |
| 文件頁數： | 52/70頁 |
| 文件大小： | 696K |
| 代理商： | GS9090-CNE3 |
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GS9090 Data Sheet
28201 - 1
July 2005
52 of 70
Clearing the ANC_PKT_EXT bit will not automatically disable ancillary data
extraction. To disable ancillary data extraction, switch the FIFO into bypass mode
by setting FIFO_MODE[1:0] = 11b. 2200 PCLK cycles after the device re-enters
ancillary data extraction mode, data extraction will commence immediately if
ANC_PKT_EXT is still HIGH.
The application layer can use the ANC_DETECT output flag available on the I/O
output pin (see
Programmable Multi-Function Outputs on page 56
) to determine
the length of the ancillary data extracted and when to begin reading the extracted
data from memory. Recall that ANC_DETECT is HIGH whenever ancillary data
has been detected.
In addition, the data count (DC) word, which is located three words after the
ancillary data flag (ADF) in the memory, can be read to determine how many valid
user data words (UDW) are present in the extracted packet (see SMPTE 291M for
more details). The DC value can then be used to preset how many address reads
must be performed to obtain only the user data words.
Ancillary data will be written into the first half of the FIFO until it is full or until the
ANC_DATA_SWITCH bit is toggled (i.e. a HIGH-to-LOW or LOW-to-HIGH
transition). If the ANC_DATA_SWITCH bit is not toggled, extracted data will not be
written into memory after the first half of the FIFO is full (see block A in
Figure 3-12
).
When the ANC_DATA_SWITCH bit is toggled, new extracted data will be written
to the second half starting at address zero (see block B in
Figure 3-12
). The data
in the first half of the FIFO may still be read.
Once the data in the first half of the FIFO has been read, the ANC_DATA_SWITCH
may be toggled again to enable the second half of the FIFO to be read. The first
half of the FIFO will be cleared, and the device will continue to write ancillary data
to the second half of the FIFO (see block C in
Figure 3-12
).
If the ANC_DATA_SWITCH bit is toggled again, new extracted data will be written
to the first half starting at address zero (see block D in
Figure 3-12
). The data in the
second half of the FIFO may still be read.
Toggling ANC_DATA_SWITCH again will clear the second half of the FIFO and
restore the read and write pointers to the situation shown in block A. The switching
process (shown in blocks A to D in
Figure 3-12
) will continue with each toggle of
the ANC_DATA_SWITCH bit.
NOTE: At least 1100 PCLK cycles (41us) must pass between toggles of the
ANC_DATA_SWITCH bit. The ANC_DATA_SWITCH bit must be toggled at a point
in the video where no extraction is occurring (i.e. the ANC_DETECT signal is
LOW).
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相關代理商/技術參數 |
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| GS9091B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX II 270Mb/s Deserializer for SDI and DVB-ASI |
| GS9091BCBE3 | 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 功能:解串器 數據速率:2.5Gbps 輸入類型:串行 輸出類型:并聯 輸入數:- 輸出數:24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應商設備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| GS9092 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092A_10 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX III 270Mb/s Serializer for SDI and DVB-ASI |
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