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參數資料
| 型號： | L64118 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數： | 17/68頁 |
| 文件大小： | 877K |
| 代理商： | L64118 |
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24
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
CERRn
Channel Data Error
Input
This active LOW input signal indicates that an
uncorrected error occurred in the preceding channel
interface. When CVALID is asserted, CERRn is latched
on the rising edge of CCLK.
CVALID
Channel Data Valid
Input
This active HIGH input signal indicates that CDATA[7:0]
and CERRn are carrying valid data. When CVALID is
asserted, a rising edge of CCLK latches the CDATA[7:0]
signals into the L64118.
MPEG Program Clock Reference (PCR) Recovery
These signals recover the Program Clock Reference (PCR). They
interface to the external VCxO, which provides the 27 MHz clock to the
decoder.
SCLK
27 MHz System Clock
Input
This input provides the clock signal to the L64118. It must
be driven by the external 27 MHz VCxO (the voltage
control input is controlled by SDET and the external
RC lter).
SDET
System Clock Sigma-Delta Control Voltage
Output
This converter output signal from a 16-bit Sigma-Delta
modulator inside the L64118 drives a simple low-pass
lter to produce an analog control voltage to an external
VCxO.
Phase-Locked Loop (PLL)
These signals supply power and ground to the internal PLL, which
generates the internal 54 MHz CPU clock from the external 27 MHz
SCLK input. The 54 MHz internal clock is then divided by two to generate
the internal 27 MHz clock used by other internal modules. Isolate the
PLLVDD and the PLLVSS signals from digital noise and digital logic on
the PCB using layout and bypass ltering techniques.
PLLVDD
PLL Analog VDD
Input
This provides a separate ltered 3.3 V to the PLL circuit
through PLLVDD so that switching noise from the digital
portion of the chip can not affect PLL stability.
118bds Page 24 Wednesday, February 3, 1999 12:37 PM
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