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L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
DMA Controller
The L64118 integrates a four-channel DMA controller that reduces a
major portion of the load the CPU might incur during data transfer
between peripheral ports, memory, and elements residing on the EBus.
One DMA channel is dedicated for data transfers between the IEEE1284
port and main memory. The other three DMA channels are general-
purpose. One general-purpose DMA channel (Channel #1) supports
transfers between PBus and Ebus devices.
In typical applications, one DMA channel can be assigned to a
SmartCard, one channel to a serial port, and one to memory to memory
data transfers.
Addressing
The MIPS architecture uses two types of addresses: virtual addresses
(used in a program), and physical addresses (that appear on an address
bus). This allows support of kernel and user modes, while combining
cacheable and noncacheable addresses.
Virtual addresses are partitioned into four, xed-size segments:
kuseg,
kseg0, kseg1, and kseg2, according to
Table 1.
Table 1
Memory Segment Address Mapping
The
kuseg addresses are accessible in user and kernel mode; they are
for use by user-mode programs, while also providing direct access
(requiring no system call) to those same addresses in kernel mode.
Because the L64118 does not have a Memory Management Unit (MMU),
kuseg addresses are mapped unchanged to physical addresses. The
L64118 does not map
kseg2; thus, kseg2 addresses cannot be used by
Virtual CPU Address [31:29]
Segment
Size
0b000–0b011
kuseg
2 Gbytes
0b100
kseg0 (cache)
512 Mbytes
0b101
kseg1 (noncache)
512 Mbytes
0b110–0b111
kseg2 (not used)
1 Gbytes
118bds Page 14 Wednesday, February 3, 1999 12:37 PM