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參數(shù)資料
| 型號： | L64118 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 21/68頁 |
| 文件大小： | 877K |
| 代理商： | L64118 |
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L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
INTn4
Interrupt
Input
This unmaskable interrupt can be used for highest priority
system needs.
INTn[3:0]
Interrupts
Input
These four external interrupts can be programmed to be
level- or edge-triggered sensitive. Interrupts INTn[3:0] are
maskable and for general-purpose use. When the
L64118 receives an interrupt, the internal CPU completes
the execution of the current instruction and jumps to a
preprogrammed location in the memory containing the
handler for this interrupt. By default, these signals are
level triggered after reset.
RDn
Read
Output
The active LOW read strobe is asserted during read
operations, and deasserted during writes.
WRn
Write Enable
Output
The active LOW write strobe is asserted during write
operations and deasserted during reads.
Miscellaneous Signals
These general signals are not necessarily associated with a specic
function or module of the L64118.
OP_MODE[1:0]
Operational Mode
Input
These signals, along with OP_MODE[2], are used as
strap options to congure various LSI Logic test modes.
For normal operation, congure OP_MODE[2:0] to
0b000. That is, OP_MODE[1:0] should be tied LOW, and
OP_MODE[2] should be pulled LOW with a 10 k
resistor.
OP_MODE[2]/PDATA_DIR
Operational Mode
Input
This signal is used as a strap option during reset in
conjunction with the OP_MODE[1:0] pins, and must be
pulled LOW with a 10 k
resistor for proper device
operation.
118bds Page 28 Wednesday, February 3, 1999 12:37 PM
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