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參數資料
| 型號： | L64118 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數： | 33/68頁 |
| 文件大小： | 877K |
| 代理商： | L64118 |
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L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 39
BUSY/AUXSB
1284 - Peripheral Busy
Bidirectional
In 1284 mode, this signal functions as BUSY. When this
signal is HIGH, the 1284 port is not ready for a data
transfer. By default, this signal is not asserted after reset.
Aux - Sync Byte
Bidirectional
In Aux mode, this signal functions as AUXSB to indicate
that the data being sent through the auxiliary port is the
rst byte (sync byte) of a transport packet.
GPIO15
Bidirectional
This signal can serve as a general-purpose I/O signal
(GPIO15) by setting bit 3 in the General-Purpose Mode
register.
FAULTn/AUXCLK
1284 - Peripheral Fault Operation
Bidirectional
In 1284 mode, this signal functions as FAULTn. This
signal indicates that the 1284 port encountered an error
during operation. Typically, this error is due to overrun,
underrun, or parity error.
Aux - Aux Port Clock
Bidirectional
In Aux mode, this signal functions as AUXCLK, which is
the reference clock for all transactions on the auxiliary
port. When the Aux port is congured as an output port,
this signal is an output with programmable frequencies of
13.5, 6.75 and 3.375 MHz. When the Aux port is
congured as an input port, this signal is an input with a
frequency based on the input transport stream data rate.
GPIO24
Bidirectional
This signal can also serve as a general-purpose I/O
signal (GPIO24) by setting bit 3 in the General-Purpose
Mode register.
INIT/AUXPID[2]
1284 - Peripheral Initialization
Input
In 1284 mode, this signal functions as INITn. When reset
LOW, this signal resets the IEEE1284 port and returns
the logic to the compatibility and idle state.
118bds Page 39 Wednesday, February 3, 1999 12:37 PM
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