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參數資料
| 型號： | L64118 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數： | 19/68頁 |
| 文件大?。?/td> | 877K |
| 代理商： | L64118 |
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L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
The byte enables always correspond to the same
physical lines on the AD bus: BEn[1] corresponds to
AD[15:8], BEn[0] to AD[7:0].
BEn[2]
Byte Enable
Output
The four byte enable outputs are asserted during a read
or write transaction on the EBus to control which of the
four byte lanes are enabled. The byte lane selection is
dependent on the width of the transaction (word,
halfword, or byte) and the data width of the external
device (32, 16, or 8 bits).
The byte enables always correspond to the same
physical lines on the AD bus: BEn[2] corresponds to
AD[23:16].
GPIO2
Bidirectional
BEn[2] can serve as a general-purpose I/O signal
(GPIO2) by setting bit 0 in the General-Purpose Mode
register.
BEn[3]
Byte Enable
Output
The four byte enable outputs are asserted during a read
or write transaction on the EBus, to control which of the
four byte lanes are enabled. The byte lane selection is
dependent on the width of the transaction (word,
halfword, or byte) and the data width of the external
device (32, 16, or 8 bits).
The byte enables always correspond to the same
physical lines on the AD bus: BEn[3] corresponds to
AD[31:24].
GPIO3
Bidirectional
BEn[3] can serve as a general-purpose I/O signal
(GPIO4) by setting bit 0 in the General-Purpose Mode
register.
CPU_CLK
EBus Output Clock
Output
This 27 MHz output clock is generated dividing the
on-chip 54 MHz clock by two. This clock serves as the
reference signal for all transactions on the EBus. The
timing relationship between the SDCLK output clock, the
27 MHz SCLK input and the 27 MHz CPU_CLK output is
unknown.
118bds Page 26 Wednesday, February 3, 1999 12:37 PM
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