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參數資料
| 型號： | LTC4268IDKD-1#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 19/46頁 |
| 文件大小： | 419K |
| 描述： | IC PD HIGH POWER W/CNTRL 32-DFN |
| 產品培訓模塊： | Power over Ethernet |
| 標準包裝： | 52 |
| 類型： | 以太網供電開關（PoE） |
| 應用： | 遠程外設（工業控制，相機，數據訪問） |
| 內部開關： | 是 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 32-DFN（7x4）裸露焊盤 |
| 包裝： | 管件 |
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42681fc
LTC4268-1
19
consume a lot of power, it is important to delay activation
of the DC/DC converter with the power good signal. If
the converter is not disabled during the current-limited
turn-on sequence, the DC/DC converter will rob current
intended for charging up the load capacitor and create a
slow rising input, possibly causing the LTC4268-1 to go
into thermal shutdown.
The active high PWRGD pin features an internal,
open-collector output referenced to V
NEG
. During inrush,
the active high PWRGD pin becomes valid when C1 reaches
4V and pulls low until the load capacitor is fully charged.
At that point, PWRGD becomes high impedance, indicating
the switching regulator may begin running. The active
high PWRGD pin interfaces directly to the UVLO pin of
the LTC4268-1 with the aid of an external pull-up resistor
to Vcc. The PWRGD pin includes an internal 14V clamp to
V
NEG
. During a power supply ramp down event, PWRGD
becomes low impedance when V
PORT
drops below the 30V
PD UVLO turn-off threshold, then goes high impedance
when the V
PORT
voltages fall to within the detection voltage
range. Figure 11 shows a typical connection scheme for
the active high PWRGD pin.
The LTC4268-1 also includes an active low PWRGD pin
for system level use. PWRGD is referenced to the V
PORTN
pin and when active will be near the V
PORTN
potential. The
negative rail (GND) of the internal switching regulator will
typically be referenced to V
NEG
and care must be taken to
ensure that the difference in potential of the PWRGD pin
does not cause a problem for the switcher.
THERMAL PROTECTION
The LTC4268-1 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
At turn-on, before load capacitor C1 has charged up, the
instantaneous power dissipated by the LTC4268-1 can be
as high as 20W. As the load capacitor charges, the power
dissipation in the LTC4268-1 will decrease until it reaches
a steady-state value dependent on the DC load current.
The LTC4268-1 can also experience device heating after
turn-on if the PD experiences a fast input voltage rise. For
example, if the PD input voltage steps from 37V to 57V,
the instantaneous power dissipated by the LTC4268-1 can
be as high as 16W. The LTC4268-1 protects itself from
damage by monitoring die temperature. If the die exceeds
the overtemperature trip point, the power MOSFET and
classification transistors are disabled until the part cools
down. Once the die cools below the overtemperature trip
point, all functions are enabled automatically. During
classification, excessive heating of the LTC4268-1 can
occur if the PSE violates the 75ms probing time limit.
In addition, the IEEE 802.3af specification requires a PD
to withstand application of any voltage from 0V to 57V
indefinitely. To protect the LTC4268-1 in these situations,
the thermal protection circuitry disables the classification
circuit and the input current if the die temperature exceeds
the overtemperature trip point. When the die cools down,
classification and input current are enabled.
Once the LTC4268-1 has charged up the load capacitor and
the PD is powered and running, there will be some residual
heating due to the DC load current of the PD flowing through
the internal MOSFET. In some high current applications,
the LTC4268-1 power dissipation may be significant. The
LTC4268-1 uses a thermally enhanced DFN package that
includes an exposed pad which should be soldered to the
GND plane for heat sinking on the printed circuit board.
MAXIMUM AMBIENT TEMPERATURE
The LTC4268-1 I
LIM_EN
pin allows the PD designer to
disable the normal operating current limit. With the normal
current limit disabled, it is possible to pass currents
as high as 1.4A through the LTC4268-1. In this mode,
significant package heating may occur. Depending on
the current, voltage, ambient temperature, and waveform
characteristics, the LTC4268-1 may shut down. To avoid
nuisance trips of the thermal shutdown, it may be necessary
to limit the maximum ambient temperature. Limiting the
die temperature to 125癈 will keep the LTC4268-1 from
hitting thermal shutdown. For DC loads the maximum
ambient temperature can be calculated as:
T
MAX
= 125 ?/DIV>
JA
" PWR (癈)
where T
MAX
is the maximum ambient operating tempera-
ture, ?/DIV>
JA
is the junction-to-ambient thermal resistance
(49癈/W), and PWR is the power dissipation for the
LTC4268-1 in Watts (I
PD
2
" R
ON
).
applicaTions inForMaTion
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