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參數資料
| 型號： | LTC4268IDKD-1#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 21/46頁 |
| 文件大小： | 419K |
| 描述： | IC PD HIGH POWER W/CNTRL 32-DFN |
| 產品培訓模塊： | Power over Ethernet |
| 標準包裝： | 52 |
| 類型： | 以太網供電開關（PoE） |
| 應用： | 遠程外設（工業控制，相機，數據訪問） |
| 內部開關： | 是 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 32-DFN（7x4）裸露焊盤 |
| 包裝： | 管件 |
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LTC4268-1
21
PD is required to accept power in either polarity on both
the data and spare inputs; therefore it is common to install
diode bridges on both inputs in order to accommodate the
different wiring configurations. Figure 9 demonstrates an
implementation of the diode bridges to minimize heating.
The IEEE 802.3af specification also mandates that the
leakage back through the unused bridge be less than 28礎
when the PD is powered with 57V.
The LTC4268-1 has several different modes of operation
based on the voltage present between the V
PORTN
and
V
PORTP
pins. The forward voltage drop of the input diodes
in a PD design subtracts from the input voltage and will
affect the transition point between modes.
The input diode bridge of a PD can consume over 4% of
the available power in some applications. Schottky diodes
can be used in order to reduce power loss. The LTC4268-1
is designed to work with both standard and Schottky
diode bridges while maintaining proper threshold points
for IEEE 802.3af compliance.
Input Capacitor
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1礔 capacitor (C14 in Figure 9) is used to
meet the AC impedance requirement.
Input
Series Resistance
Linear Technology has seen the customer community cable
discharge requirements increase by nearly 500,000 times
the original test levels. The PD must survive and operate
reliably not only when an initially charged cable connects
and dissipates the energy through the PD front end, but
also when the electrical power system grounds are subject
to very high energy events (e.g., lightning strikes).
In these high energy events, adding 10?series resistance
into the V
PORTP
pin greatly improves the robustness of
the LTC4268-1 based PD (see Figure 9). The TVS limits
the voltage across the port while the 10?and 0.1礔 ca-
pacitance reduces the edge rate the LT4268-1 encounters
across its pin. The added 10?series resistance does not
operationally affect the LTC4268-1 PD Interface, nor does
it affect its compliance with the IEEE 802.3 standard.
Transient Voltage Suppressor
The LTC4268-1 specifies and absolute maximum volt-
age of 100V and is designed to tolerate brief overvoltage
events. However, the pins that interface to the outside
world can routinely see excessive peak voltages. To pro-
tect the LTC4268-1, install a transient voltage suppressor
(D3) between the input diode bridge and the LTC4268-1,
as shown in Figure 9. An SMAJ58A is recommended for
typical PD applications. However, an SMBJ58A may be
preferred in applications where the PD front end must
absorb higher energy discharge events.
Auxiliary Power Source
In some applications, it may be necessary to power the
PD from an auxiliary power source such as a wall adapter.
The auxiliary power can be injected into the PD at several
locations and various trade-offs exist. Figure 10 demon-
strates four methods of connecting external power to a PD.
Option 1 in Figure 10 inserts power before the LTC4268-1
interface controller. In this configuration, it is necessary
for the wall adapter to exceed the LTC4268-1 UVLO turn-
on requirement. This option provides input current limit
for the adapter, provides a valid power good signal and
simplifies power priority issues. As long as the adapter
applies power to the PD before the PSE, it will take priority
and the PSE will not power up the PD because the external
power source will corrupt the 25k signature. If the PSE
is already powering the PD, the adapter power will be in
parallel with the PSE. In this case, priority will be given to
the higher supply voltage. If the adapter voltage is higher,
the PSE may
remove the port voltage since no current will
be drawn from the PSE. On the other hand, if the adapter
voltage is lower, the PSE will continue to supply power to
the PD and the adapter will not be used. Proper operation
will occur in either scenario.
Option 2 applies power directly to the DC/DC converter.
In this configuration the adapter voltage does not need
to exceed the LTC4268-1 turn-on UVLO requirement and
can be selected based solely on the PD load requirements.
It is necessary to include diode D9 to prevent the adapter
from applying power to the LTC4268-1. Power priority
issues require more intervention. If the adapter voltage
is below the PSE voltage, then the priority will be given
applicaTions inForMaTion
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相關代理商/技術參數 |
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| LTC4268IDKD-1-TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:High Power PD with Synchronous NoOpto Flyback Controller |
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