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參數資料
| 型號： | LTC4268IDKD-1#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 26/46頁 |
| 文件大小： | 419K |
| 描述： | IC PD HIGH POWER W/CNTRL 32-DFN |
| 產品培訓模塊： | Power over Ethernet |
| 標準包裝： | 52 |
| 類型： | 以太網供電開關（PoE） |
| 應用： | 遠程外設（工業控制，相機，數據訪問） |
| 內部開關： | 是 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 32-DFN（7x4）裸露焊盤 |
| 包裝： | 管件 |
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LTC4268-1
26
42681fc
The flyback voltage is scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
amplifier compares the voltage to the internal bandgap
reference. The feedback amp is actually a transconductance
amplifier whose output is connected to V
CMP
only during
a period in the flyback time. An external capacitor on
the V
CMP
pin integrates the net feedback amp current to
provide the control voltage to set the current mode trip
point. The regulation voltage at the FB pin is nearly equal
to the bandgap reference V
FB
because of the high gain in
the overall loop. The relationship between V
FLBK
and V
FB
is expressed as:
V
FLBK
=
R1+R2
R2
V
FB
Combining this with the previous V
FLBK
expression yields
an expression for V
OUT
in terms of the internal reference,
programming resistors and secondary resistances:
V
OUT
=
R1+R2
R2
V
FB
N
SF
?/DIV>
?/DIV>
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?/DIV>
?/DIV>
?/DIV>
?/DIV>
I
SEC
ESR+R
DS(ON)
(
)
The effect of nonzero secondary output impedance is
discussed in further detail; see Load Compensation Theory.
The practical aspects of applying this equation for V
OUT
are found in the Applications Information.
Feedback Amplifier Dynamic Theory
So far, this has been a pseudo-DC treatment of flyback
feedback amplifier operation. But the flyback signal is a
pulse, not a DC level. Provision is made to turn on the
flyback amplifier only when the flyback pulse is present
using the enable signal as shown in the timing diagram
(Figure 13).
Minimum Output Switch On Time (t
ON(MIN)
)
The LTC4268-1 affects output voltage regulation via
flyback pulse action. If the output switch is not turned on,
there is no flyback pulse and output voltage information
is not available. This causes irregular loop response and
start-up/latch-up problems. The solution is to require
the primary switch to be on for an absolute minimum
time per each oscillator cycle. To accomplish this the
current limit feedback is blanked each cycle for t
ON(MIN)
.
If the output load is less than that developed under these
conditions, forced continuous operation normally occurs.
See Applications Information for further details.
Enable Delay Time (ENDLY)
The flyback pulse appears when the primary side switch
shuts off. However, it takes a finite time until the transformer
primary side voltage waveform represents the output
voltage. This is partly due to rise time on the primary
applicaTions inForMaTion
PRIMARY SIDE
MOSFET DRAIN
VOLTAGE
PG VOLTAGE
SG VOLTAGE
V
IN
t
ON(MIN)
ENABLE
DELAY
MIN ENABLE
FEEDBACK
AMPLIFIER
ENABLED
PG DELAY
42681 F13
V
FLBK
0.8 " V
FLBK
Figure 13. LTC4268-1 Switching Regulator Timing Diagram
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相關代理商/技術參數 |
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| LTC4268IDKD-1-TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:High Power PD with Synchronous NoOpto Flyback Controller |
| LTC4268IDKD-1-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:High Power PD with Synchronous NoOpto Flyback Controller |
| LTC4269-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:IEEE 802.3at PD with Synchronous No-Opto Flyback Controller |
| LTC4269-2 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:IEEE 802.3at High Power PD and Synchronous Forward Controller with AUX Support |
| LTC4269CDKD-1#PBF | 功能描述:IC PD/OPTO FLYBACK CTRLR 32-DFN RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 標準包裝:50 系列:- 類型:熱交換控制器 應用:-48V 遠程電力系統，AdvancedTCA ? 系統，高可用性 內部開關:無 電流限制:可調 電源電壓:11.5 V ~ 14.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-TFSOP，10-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:10-MSOP 包裝:管件 |
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