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參數資料
| 型號： | LTC4268IDKD-1#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 23/46頁 |
| 文件大小： | 419K |
| 描述： | IC PD HIGH POWER W/CNTRL 32-DFN |
| 產品培訓模塊： | Power over Ethernet |
| 標準包裝： | 52 |
| 類型： | 以太網供電開關（PoE） |
| 應用： | 遠程外設（工業控制，相機，數據訪問） |
| 內部開關： | 是 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 32-DFN（7x4）裸露焊盤 |
| 包裝： | 管件 |
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LTC4268-1
23
to the PSE power. The PD will draw power from the PSE
while the adapter will remain unused. This configuration is
acceptable in a typical PoE system. However, if the adapter
voltage is higher than the PSE voltage, the PD will draw
power from the adapter. In this situation, it is necessary to
address the issue of power cycling that may occur if a PSE
is present. The PSE will detect the PD and apply power. If
the PD is being powered by the adapter, then the PD will
not meet the minimum load requirement and the PSE may
subsequently remove power. The PSE will again detect the
PD and power cycling will start. With an adapter voltage
above the PSE voltage, it is necessary to either disable the
signature as shown in option 2, or install a minimum load
on the output of the LTC4268-1 to prevent power cycling.
A 3k, 1W resistor connected between V
PORTP
and V
NEG
will present the required minimum load.
Option 3 applies power directly to the DC/DC converter
bypassing the LTC4268-1 and omitting diode D9. With
the diode omitted, the adapter voltage is applied to the
LTC4268-1 in addition to the DC/DC
converter. For this
reason, it is necessary to ensure that the adapter maintain
the voltage between 42V and 57V to keep the LTC4268-1
in its normal operating range. The third option has the
advantage of corrupting the 25k signature resistance when
the external voltage exceeds the PSE voltage and thereby
solving the power priority issue.
Option 4 bypasses the entire PD interface and injects
power at the output of the low voltage power supply. If
the adapter output is below the low voltage output there
are no power priority issues. However, if the adapter is
above the internal supply, then option 4 suffers from the
same power priority issues as option 2 and the signature
should be disabled or a minimum load should be installed.
Shown in option 4 is one method to disable to the signature
while maintaining isolation.
If employing options 1 through 3, it is necessary to ensure
that the end-user cannot access the terminals of the aux-
iliary power jack on the PD since this would compromise
IEEE 802.3af isolation requirements and may violate local
applicaTions inForMaTion
safety codes. Using option 4 along with an isolated power
supply addresses the isolation issue and it is no longer
necessary to protect the end-user from the power jack.
The above power cycling scenarios have assumed the
PSE is using DC disconnect methods. For a PSE using
AC disconnect, a PD with less than minimum load will
continue to be powered.
Wall adapters have been known to generate voltage spikes
outside their expected operating range. Care should be
taken to ensure no damage occurs to the LTC4268-1
or any support circuitry from extraneous spikes at the
auxiliary power interface.
Classification Resistor Selection (R
CLASS
)
The IEEE 802.3af specification allows classifying PDs into
four distinct classes with class 4 being reserved for future
use (Table 2). The LTC4268-1 supports all IEEE classes
and implements an additional Class 5 for use in custom
PoE applications. An external resistor connected from
R
CLASS
to V
PORTN
(Figure 6) sets the value of the load
current. The designer should determine which class the
PD is to advertise and then select the appropriate value of
R
CLASS
from Table 2. If a unique load current is required,
the value of R
CLASS
can be calculated as:
R
CLASS
= 1.237V/(I
LOAD
I
IN_CLASS
)
I
IN_CLASS
is the LTC4268-1 IC supply current during
classification given in the electrical specifications. The
R
CLASS
resistor must be 1% or better to avoid degrading
the overall accuracy of the classification circuit. Resis-
tor power dissipation will be 100mW maximum and is
transient so heating is typically not a concern. In order
to maintain loop stability, the layout should minimize
capacitance at the R
CLASS
node. The classification circuit
can be disabled by floating the R
CLASS
pin. The R
CLASS
pin
should not be shorted to V
PORTN
as this would force the
LTC4268-1 classification circuit to attempt to source very
large currents. In this case, the LTC4268-1 will quickly go
into thermal shutdown.
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