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參數資料
| 型號： | LTC4268IDKD-1#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 34/46頁 |
| 文件大小： | 419K |
| 描述： | IC PD HIGH POWER W/CNTRL 32-DFN |
| 產品培訓模塊： | Power over Ethernet |
| 標準包裝： | 52 |
| 類型： | 以太網供電開關（PoE） |
| 應用： | 遠程外設（工業控制，相機，數據訪問） |
| 內部開關： | 是 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 32-DFN（7x4）裸露焊盤 |
| 包裝： | 管件 |
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LTC4268-1
34
42681fc
minimum on time along with synchronous rectification
sets the switch over to forced continuous mode operation.
The t
ON(MIN)
resistor is set with the following equation
R
tON(MIN)
kW
( )
=
t
ON(MIN)
ns
( )
104
1.063
Keep R
tON(MIN)
greater than 70k. A good starting value
is 160k.
Enable Delay Time (ENDLY)
Enable delay time provides a programmable delay between
turn-off of the primary gate drive node and the subsequent
enabling of the feedback amplifier. As discussed earlier, this
delay allows the feedback amplifier to ignore the leakage
inductance voltage spike on the primary side. The worst-case
leakage spike pulse width is at maximum load conditions.
So set the enable delay time at these conditions.
While the typical applications for this part use forced
continuous operation, it is conceivable that a secondary
side controller might cause discontinuous operation at
light loads. Under such conditions the amount of energy
stored in the transformer is small. The flyback waveform
becomes lazy and some time elapses before it indicates
the actual secondary output voltage. The enable delay time
should be made long enough to ignore the irrelevant
portion of the flyback waveform at light loads.
Even though the LTC4268-1 has a robust gate drive, the
gate transition time slows with very large MOSFETs. In-
crease delay time as required when using such MOSFETs.
The enable delay resistor is set with the following equation:
R
ENDLY
kW
( )
=
t
ENDLY
ns
( )30
2.616
Keep R
ENDLY
greater than 40k. A good starting point is 56k.
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of
the primary side MOSFET. Correct setting eliminates
overlap between the primary side switch and secondary
side synchronous switch(es) and the subsequent current
spike in the transformer. This spike will cause additional
component stress and a loss in regulator efficiency.
The primary gate delay resistor is set with the following
equation:
R
PGDLY
kW
( )
=
t
PGDLY
ns
( )
+ 47
9.01
A good starting point is 27k.
Soft-Start Function
The LTC4268-1 contains an optional soft-start function that
is enabled by connecting an external capacitor between
the SFST pin and ground. Internal circuitry prevents the
control voltage at the V
CMP
pin from exceeding that on
the SFST pin. There is an initial pull-up circuit to quickly
bring the SFST voltage to approximately 0.8V. From there it
charges to approximately 2.8V with a 20礎 current source.
The SFST node is discharged to 0.8V when a fault occurs.
A fault occurs when V
CC
is too low (undervoltage lockout),
current sense voltage is greater than 200mV or the ICs
thermal (over temperature) shutdown is tripped. When
SFST discharges, the V
CMP
node voltage is also pulled low
to below the minimum current voltage. Once discharged
and the fault removed, the SFST charges up again. In this
manner, switch currents are reduced and the stresses in
the converter are reduced during fault conditions.
The time it takes to fully charge soft-start is:
t
ss
=
C
SFST
1.4V
20礎
=70kW C
SFST
礔
( )
applicaTions inForMaTion
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相關代理商/技術參數 |
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| LTC4268IDKD-1-TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:High Power PD with Synchronous NoOpto Flyback Controller |
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| LTC4269CDKD-1#PBF | 功能描述:IC PD/OPTO FLYBACK CTRLR 32-DFN RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 標準包裝:50 系列:- 類型:熱交換控制器 應用:-48V 遠程電力系統，AdvancedTCA ? 系統，高可用性 內部開關:無 電流限制:可調 電源電壓:11.5 V ~ 14.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-TFSOP，10-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:10-MSOP 包裝:管件 |
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