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參數資料
| 型號： | MPC823 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Communication Processor Module |
| 中文描述： | 通信處理器模塊 |
| 文件頁數： | 17/74頁 |
| 文件大小： | 234K |
| 代理商： | MPC823 |
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Communication Processor Module
MOTOROLA
MPC823 REFERENCE MANUAL
16-395
S
C
1
P
16.11.6.10 SMCx UART MODE REGISTER.
When a serial management controller is in
UART mode, the 16-bit, memory-mapped, read/write SMCx mode register is referred to as
the SMCx UART mode register (SMCMR–UART). The functionality of bits 8-15 is common
to each SMCx protocol, but bits 0-7 vary according to the protocol selected by the SM field.
This register is cleared by reset.
Bits 0 and 8–9—Reserved
These bits are reserved and must be set to 0.
CLEN—Character Length
This field must be programmed with the total number of bits in the character minus one. The
total number of bits in the character is calculated as the sum of 1 (start bit always present)
+ number of data bits (5 to 14) + number of parity bits (0 or 1) + number of stop bits (1 or 2).
For example, for 8 data bits, no parity, and 1 stop bit, the total number of bits in the character
is 1 + 8 + 0 + 1 = 10. In this case, CLEN must be programmed to 9.
The number of data bits in the character ranges from 5 to 14 bits. If the data bit length is less
than 8 bits, the most-significant bits of each byte in memory are not used on transmission
and are written with zeros on reception. On the other hand, if the data bit length is more than
8 bits, the most-significant bits of each 16-bit word in memory are not used on transmit and
are written with zeros on receive.
SL—Stop Length
0 = One stop bit.
1 = Two stop bits.
PEN—Parity Enable
0 = No parity.
1 = Parity is enabled for the transmitter and receiver, depending on the PM bit setting.
SMCMR–UART
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIELD
RES
CLEN
SL
PEN
PM
RES
SM
DM
TEN
REN
RESET
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0xA82 (SMC1), 0xA92 (SMC2)
Note:
The total number of bits in the character must never exceed 16. Thus, if you
choose a 14-bit data length, set SL to one stop bit and disable parity. If you
choose a 13-bit data length and parity is enabled, set SL to one stop bit. To
prevent erratic behavior, do not write the values 0-3 to CLEN.
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