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參數資料
| 型號： | MPC823 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Communication Processor Module |
| 中文描述： | 通信處理器模塊 |
| 文件頁數： | 6/74頁 |
| 文件大?。?/td> | 234K |
| 代理商： | MPC823 |
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Communication Processor Module
16-384
MPC823 REFERENCE MANUAL
MOTOROLA
S
C
1
P
RBASE and TBASE—These entries are used by the dual-port RAM starts the SMCx
receive and transmit buffer descriptors. They provide a great deal of flexibility for
partitioning the buffer descriptors for a serial management controller. By selecting
RBASE and TBASE entries for a serial management controller and by setting the W bit
in the last buffer descriptor in each buffer descriptor list, you can select the number of
buffer descriptors to allocate for the transmit and receive side of the serial management
controller. However, you must initialize these entries before enabling the corresponding
channel. Furthermore, you must not configure buffer descriptor tables of two enabled
serial management controllers to overlap or erratic operation will occur.
RFCR and TFCR—There are separate function code registers for the two SMCx
channels. One for receive data buffers (RFCR) and one for transmit data buffers
(TFCR). The function code entry contains the value that you want to appear on the AT
pins when the associated SDMA channel accesses memory. It also controls the
byte-ordering convention that is used in the transfers.
Bits 0–2—Reserved
These bits are reserved and must be set to 0.
BO—Byte Ordering
Set these bits to select the required byte ordering of the data buffer. If this field is
modified on-the-fly, it takes effect at the beginning of the next frame or the next buffer
descriptor.
00 =
The DEC/Intel convention is used for byte ordering (swapped operation) and
is also called little-endian byte ordering. The transmission order of bytes within
a buffer word is reversed in comparison to the Motorola mode. This mode is
supported only for 32-bit port size memory.
Note:
RBASE and TBASE must contain a value that is divisible by eight.
RFCR
BIT
0
1
2
3
4
5
6
7
FIELD
RESERVED
BO
AT1-AT3
RESET
0
0
0
R/W
R/W
R/W
R/W
ADDR
SMC1 AND SMC2 BASE + 0x04
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