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參數(shù)資料
| 型號： | S29CL032J0RFFN130 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件頁數(shù)： | 18/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CL032J0RFFN130 |
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September 27, 2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
23
Pr el im i n a r y
Figure 8.2 Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions:
tIACC specification: The time from the rising edge of the first clock
cycle after addresses are latched to valid data on the device out-
puts.
Configuration register setting CR13-CR10: The total number of
clock cycles (wait states) that occur before valid data appears on
the device outputs. The effect is that tIACC is lengthened.
Like the main memory access, the Secured Silicon Sector memory is accessed with the same
burst or asynchronous timing as defined in the Configuration Register. However, the user must
recognize burst operations past the 256 byte Secured Silicon boundary returns invalid data.
Burst read operations occur only to the main flash memory arrays. The Configuration Register
and protection bits are treated as single cycle reads, even when burst mode is enabled. Read
operations to these locations results in the data remaining valid while OE# is at VIL, regardless
of the number of CLK cycles applied to the device.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Synchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(D15 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(D15 = 1)
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