- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄192296 > S29CL032J0RFFN130 (SPANSION LLC) 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 PDF資料下載
參數(shù)資料
| 型號： | S29CL032J0RFFN130 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件頁數(shù)： | 72/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CL032J0RFFN130 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁當(dāng)前第72頁第73頁第74頁第75頁第76頁第77頁第78頁
72
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
Prel imi n ary
Table 20.2 Sector Protection Command Definitions (x32 Mode)
Command (Notes)
Cy
cl
es
First
Second
Third
Fourth
Fifth
Sixth
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Reset
1
XXX
F0
Secured Silicon Sector Entry
3
555
AA
2AA
55
555
88
Secured Silicon Sector Exit
4
555
AA
2AA
55
555
90
XX
00
Secured Silicon Protection
Bit Program (5, 6)
6
555
AA
2AA
55
555
60
OW
68
OW
48
OW
RD(0)
Secured Silicon Protection Bit Status
6
555
AA
2AA
55
555
60
OW
RD(0)
Password Program (5, 7, 8)
4
555
AA
2AA
55
555
38
PWA[0-1]
PWD[0-1]
Password Verify
4
555
AA
2AA
55
555
C8
PWA[0-1]
PWD[0-1]
Password Unlock (7, 8)
5
555
AA
2AA
55
555
28
PWA[0-1]
PWD[0-1]
6
555
AA
2AA
55
555
60
SG+WP
68
SG+WP
48
SG+WP
RD(0)
All PPB Erase (5, 9, 10)
6
555
AA
2AA
55
555
60
WP
60
WP
40
WP
RD(0)
PPB Status (11, 12)
4
555
AA
2AA
55
BA+555
90
SA+X02
00/01
PPB Lock Bit Set
3
555
AA
2AA
55
555
78
PPB Lock Bit Status
4
555
AA
2AA
55
BA+555
58
SA
RD(1)
DYB Write (7)
4
555
AA
2AA
55
555
48
SA
X1
DYB Erase (7)
4
555
AA
2AA
55
555
48
SA
X0
DYB Status (12)
4
555
AA
2AA
55
BA+555
58
SA
RD(0)
PPMLB Program (5, 6)
6
555
AA
2AA
55
555
60
PL
68
PL
48
PL
RD(0)
PPMLB Status (5)
6
555
AA
2AA
55
555
60
PL
RD(0)
SPMLB Program (5, 6)
6
555
AA
2AA
55
555
60
SL
68
SL
48
SL
RD(0)
SPMLB Status (5)
6
555
AA
2AA
55
555
60
SL
RD(0)
Legend:
DYB = Dynamic Protection Bit
OW = Address (A5–A0) is (011X10).
PPB = Persistent Protection Bit
PWA = Password Address. A0 selects between the low and high 32-bit
portions of the 64-bit Password
PWD = Password Data. Must be written over two cycles.
PL = Password Protection Mode Lock Address (A5–A0) is (001X10)
RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0= 1,
if unprotected, DQ0 = 0.
RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 =
1, if unprotected, DQ1 = 0.
SA = Sector Address. The set of addresses that comprise a sector. The
system may write any address within a sector to identify that sector
for a command.
SG = Sector Group Address
BA = Bank Address. The set of addresses that comprise a bank. The
system may write any address within a bank to identify that bank for a
command.
SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)
WP = PPB Address (A5–A0) is (111010)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
Notes:
1. See Table 8.1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are
write operations.
4. During unlock cycles, (lower address bits are 555 or 2AAh as
shown in table) address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
5. The reset command returns the device to reading the array.
6. The fourth cycle programs the addressed locking bit. The fifth
and sixth cycles are used to validate whether the bit has been
fully programmed. If DQ0 (in the sixth cycle) reads 0, the
program command must be issued and verified again.
7. Data is latched on the rising edge of WE#.
8. The entire four bus-cycle sequence must be entered for each
portion of the password.
9. The fourth cycle erases all PPBs. The fifth and sixth cycles are
used to validate whether the bits have been fully erased. If DQ0
(in the sixth cycle) reads 1, the erase command must be issued
and verified again.
10. Before issuing the erase command, all PPBs should be
programmed in order to prevent over-erasure of PPBs.
11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not
set.
12. The status of additional PPBs and DYBs may be read (following
the fourth cycle) without reissuing the entire command
sequence.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29CL032J1JFAI110 | 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CL032J1MFAN120 | 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CL032J0PQAN102 | 1M X 32 FLASH 3.3V PROM, 54 ns, PQFP80 |
| S29GL016A10FAI020 | 1M X 16 FLASH 3V PROM, 100 ns, PBGA64 |
| S29GL032A10TAIR10 | 64 MEGABIT 32MEGABIT 3.0 BOLT ONLY PAGE MODE FLASH MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29GL016A | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL016A100BAI010 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL016A100BAI012 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL016A100BAI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL016A100BAIR10 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。