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參數資料
| 型號： | S29CL032J0RFFN130 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件頁數： | 32/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CL032J0RFFN130 |
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36
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
Prel imi n ary
After an erase command sequence is written, if all sectors selected for erasing are protected,
DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sec-
tors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after
the program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program Algorithm is complete.
See Figure 18.12, Toggle Bit Timings (During Embedded Algorithms), on page 64 for additional
information.
8.8.3
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence. DQ2 toggles when the system performs two consecutive reads at addresses within
those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for
erasure. Thus, both status bits are required for sector and mode information. Refer to Table 8.8
to compare outputs for DQ2 and DQ6. See DQ6: Toggle Bit I on page 35 for additional
information.
8.8.4
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must perform two consecutive
reads of DQ7-DQ0 in a row in order to determine whether a toggle bit is toggling. Typically, the
system notes and stores the value of the toggle bit after the first read. After the second read,
the system compares the new value of the toggle bit with the first. If the toggle bit is not tog-
gling, the device completes the program or erases operation. The system can read array data on
DQ7-DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still tog-
gling, the system also notes whether the value of DQ5 is high (see the section on DQ5). If it is,
the system then determines again whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erases operation. If it is still toggling, the device had
not completed the operation successfully, and the system writes the reset command to return to
reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through
successive read cycles, determining the status as described in the previous paragraph. Alterna-
tively, the system may choose to perform other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to determine the status of the operation. Refer
to Figure 8.8 for more on the Toggle Bit Algorithm.
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