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參數資料
| 型號： | S29CL032J0RFFN130 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件頁數： | 65/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CL032J0RFFN130 |
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66
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
Prel imi n ary
18.7 Alternate CE# Controlled Erase/Program Operations
Notes:
1. Not 100% tested.
2. See Command Definitions on page 71 for more information.
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 18.16 Alternate CE# Controlled Write Operation Timings
Parameter
Description
All Speed
Options
Unit
JEDEC
Std.
tAVAV
tWC
Write Cycle Time (Note 1)
Min
65
ns
tAVEL
tAS
Address Setup Time
Min
0
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
35
ns
tEHDX
tDH
Data Hold Time
Min
2
ns
tGHEL
Read Recovery Time Before Write(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tWP
WE# Width
Min
25
ns
tELEH
tCP
CE# Pulse Width
Min
20
ns
tEHEL
tCPH
CE# Pulse Width High
Min
30
ns
tWHWH1
tWHWH1 Programming Operation (Note 2)
Double-Word
Typ
9
s
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
0.5
sec
tWADVS WE# Rising Edge Setup to ADV# Falling Edge
Min
11.75
ns
tWCKS
WE# Rising Edge Setup to CLK Rising Edge
Min
5
ns
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
tDH
tCP
DQ7#
DOUT
tWC
tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
tBUSY
tWPH
tWP
Addresses
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