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參數資料
| 型號： | TFP420PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, POWER, THERMALLY ENHANCED, PLASTIC, TQFP-64 |
| 文件頁數： | 15/20頁 |
| 文件大?。?/td> | 253K |
| 代理商： | TFP420PAP |
TFP420
PanelBus
DIGITAL TRANSMITTER
SLDS123A – MARCH 2000 – REVISED JUNE 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
POWER
RAIL
NO.
I/O
DESCRIPTION
DVI Output
TX2+
TVDD
28
A
Red channel positive transmitter output – Positive side of red channel T.M.D.S. low voltage signal
differential output pair. Red channel transmits red pixel data in active display and 00 control bits in blank.
TX2–
TVDD
27
A
Red channel negative transmitter output – Negative side of red channel T.M.D.S. low voltage signal
differential output pair.
TX1+
TVDD
25
A
Green channel positive transmitter output – Positive side of green channel T.M.D.S. low voltage signal
differential output pair. Green channel transmits green pixel data in active display and 00 control bits in
blank.
TX1–
TVDD
24
A
Green channel negative transmitter output – Negative side of green channel T.M.D.S. low voltage signal
differential output pair.
TX0+
TVDD
22
A
Blue channel positive transmitter output – Positive side of blue channel T.M.D.S. low voltage signal
differential output pair. Blue channel transmits blue pixel data in active display and HSYNC, VSYNC
control signals in blank.
TX0–
TVDD
21
A
Blue channel negative transmitter output – Negative side of blue channel T.M.D.S. low voltage signal
differential output pair.
TXC+
TVDD
30
A
Clock positive transmitter output – Positive side of reference clock T.M.D.S. low voltage signal
differential output pair.
TXC–
TVDD
31
A
Clock negative transmitter output – Negative side of reference clock T.M.D.S. low voltage signal
differential output pair.
TFADJ
TVDD
19
A
T.M.D.S. drivers full scale adjust control
A 2-k
resistor must be connected between this terminal and TVSS.
I2C Interface and Miscellaneous
A0
DVCC
10
I
I2C slave address select
GPIO0
DVCC
18
I/O
General-purpose I/O #0
First general-purpose I/O. This terminal has an internal weak pulldown of 1 M
(TBD). With GPIO0 as
an input, use an external 10 k
resistor to pull up or down to set the state of this terminal.
HS/CS/
GPIO1
AVCC
45
I/O
Digital horizontal sync output – This is the HSYNC signal that connects to the VGA connector.
Digital composite sync output – Composite HSYNC and VSYNC. The polarity of this signal is
programmable when used for HS/CS.
General-purpose I/O #1 – Second general-purpose I/O. This terminal has an internal weak pulldown of
1 M
(TBD). With GPIO1 as an input, use an external 10-k resistor to pull up or down to set the state of
this terminal.
HTPLG
DVCC
11
I
DVI/P&D/DFP hot plug detect input
NC
AVCC
38–41,
43, 44
A
Reserved
RST
DVCC
13
I
Reset signal active low.
SCL
DVCC
15
I/O
I2C serial clock input maximum. Clock rate of 400 kHz. Open drained I/O.
SDA
DVCC
14
I/O
I2C Serial data line open drained I/O.
TEST
DVCC
17
I
Test mode enable
This terminal must be tied to LOW for normal mode of operation. Connecting this terminal to HIGH puts
TFP420 in test mode.
VS
AVCC
46
O
Digital vertical sync output
When the analog RGB video output is enabled this signal is the VSYNC that connects to the VGA
connector.
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