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參數資料
| 型號： | TFP420PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, POWER, THERMALLY ENHANCED, PLASTIC, TQFP-64 |
| 文件頁數： | 19/20頁 |
| 文件大小： | 253K |
| 代理商： | TFP420PAP |
TFP420
PanelBus
DIGITAL TRANSMITTER
SLDS123A – MARCH 2000 – REVISED JUNE 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
video port (continued)
To ease the timing and EMI issues associated with a high pixel transfer rate, the signaling level of the signals
in video port is scalable. The input signals in video port are scalable by adjusting the voltage on the VREF terminal
to VDDQ/2. Similarly, the output signals are scalable by adjusting the voltage on the VDDQ terminal to VDDQ,
where VDDQ is the desirable full-swing voltage for the video port I/O signals. The differential CLKIN pair
provides more robust and reliable sampling for the pixel data and control signals, alleviating tight setup and hold
time requirements for high pixel transfer rates. Although differential clocking is the recommended clocking
scheme, it is possible to use single-end clocking with reduced timing margin, which may be significant with high
clock rates. When single-end clocking is used, CLKIN0 must be connected to the clock and CLKIN1 must be
connected to VDDQ/2.
The INT1 terminal, when enabled, generates an interrupt to inform the host CPU of events related to hot plug
and power management. INT1 is open-drained and must be pulled up to VDDQ with a 10-K
resistor.
The INT0 terminal provides a dedicated interrupt for future applications. Similar to INT1, INT0 is open-drained.
Normally a 10-K
pullup resistor is needed to pull the signal to VDDQ. The TFP420 enters a special mode when
the INT0 is forced to low just before the deassertion of the RST.
DVI encoder
The DVI encoder receives RGB pixel data from the video port and encodes the pixel data based on the transition
minimized differential signaling (T.M.D.S.) encoding algorithm. The DVI encoder consists of three independent
identical channels, each of which is responsible for encoding one color component. The encoding algorithm
minimizes the signal transition while maintaining a good dc balance to reduce EMI. The encoded data is then
serially shifted to the DVI output drivers for transmission. The low-voltage swing differential output further
reduces EMI.
Each channel is encoded independently. Each channel receives 2 bits of control data and 8 bits of color
component data. Depending on the state of BLANK, the DVI encoder encodes either control data or color
components. In either case, the data is encoded to a 10-bit character and serially shifted out with the LSB
transmitted first. Blue channel (Channel 0) receives HSYNC and VSYNC as the control data and the blue color
component as the pixel data. If BLANK is low, indicating valid blue component data is not transmitting, the DVI
encoder of the blue channel encodes the HSYNC and VSYNC signals. If BLANK is high, indicating valid blue
component data is transmitting, the DVI encoder encodes the blue component data. The green channel
(Channel1) and the red channel (Channel 2) operate in a way similar to the blue channel with the exception that
the control bits are hardwired to 0.
There are two possible encoded characters for each pixel data. The DVI encoder keeps track of the difference
between the number of ones and zeros that have been sent and selects the character that minimizes the
difference in order to maintain the best dc balance.
A serializer serializes the 10-bit character in each channel. An on-chip PLL locks to the CLKIN0 and CLKIN1
and generates the 10X clock to drive the serializer. The 10X clock is also sent to the T.M.D.S. drivers for output.
clock generation
The TFP420 uses the CLKIN signal to generate the required clock for DVI output. The on-chip PLL takes CLKIN
as the reference and generates the 10X clock. This clock is used internally by the DVI encoder to encode and
clock out the DVI bit stream as well as to output TXC+ and TXC– differential clock along with the DVI data
signals.
The CLK_CTRL register provides additional control over the clock signals. DKEN and CLKINDSK[2:0] allow the
user to compensate the skew between the CLKIN and the pixel data and control signals. Refer to the description
of the CLK_CTRL for details.
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