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參數(shù)資料
| 型號： | TFP420PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, POWER, THERMALLY ENHANCED, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大小： | 253K |
| 代理商： | TFP420PAP |
TFP420
PanelBus
DIGITAL TRANSMITTER
SLDS123A – MARCH 2000 – REVISED JUNE 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description
overview
The TFP420 integrates a PLL, DVI encoder, and three differential pairs of T.M.D.S. drivers. A dedicated
high-speed low terminal count video pixel port transfers high-bandwidth digital video data from a graphics
controller or other digital video source to the TFP420.
The TFP420 is versatile and highly programmable to provide maximum flexibility for the user. An I2C host
interface is provided to program and configure the TFP420.
I2C interface
The I2C interface is used to access the internal TFP420 register. This two-terminal interface consists of one
clock line, SCL, and one serial data line, SDA. The basic I2C access cycles are shown in Figures 1 and 2.
SDA
Start Condition (S)
Stop Condition (P)
SCL
Figure 1. I2C Start and Stop Conditions
The basic access cycle consists of the following:
D A start condition
D A slave address cycle
D A subaddress cycle
D Any number of data cycles
D A stop condition
The start and stop conditions are shown in Figure 2. The high to low transition of SDA while SCL is high defines
the start condition. The low to high transition of SDA while SCL is high defines the stop condition. Each cycle,
data or address consists of 8 bits of serial data followed by one acknowledge bit generated by the receiving
device. Thus, each data/address cycle contains 9 bits as shown in Figure 2.
SCL
1
2
3
4
5
6
7
8
9
SCL
SDA
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
1
Slave Address
MSB
Subaddress
Data
Stop
Figure 2. I2C Access Cycles
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