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參數資料
| 型號： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁數： | 121/165頁 |
| 文件大小： | 1895K |
| 代理商： | TLV320AIC36IZQE |
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÷N
BCLK
DAC_CLK
ADC_MOD_CLK
DAC_MOD_CLK
ADC_CLK
BDIV_CLKIN
N=1,2,...,127,128
www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
Table 5-19. CODEC CLKIN Clock Dividers (continued)
Divider
Bits
AOSR
Page 0, Register 20, D(7:0)
The DAC Modulator is clocked by DAC_MOD_CLK. For proper power-up operating of the DAC Channel,
these clocks must be enabled by configuring the NDAC and MDAC clock dividers (Page 0, Register 11,
D(7) =1 and Page 0, Register 12, D(7)=1). When the DAC channel is powered down, the device internally
initiates a power-down sequence for proper shut-down. During this shut-down sequence, the NDAC and
MDAC dividers must not be powered down, or else a proper low power shut-down may not take place.
The user can read back the power-status flag Page 0, Register 37, D(7) and Page 0, Register 37, D(3).
When both the flags indicate power-down, the MDAC divider may be powered down, followed by the
NDAC divider.
The ADC modulator is clocked by ADC_MOD_CLK. For proper power-up of the ADC Channel, these
clocks are enabled by the NADC and MADC clock dividers (Page 0, Register 18, D(7) =1 and Page 0,
Register 19, D(7)=1). When the ADC channel is powered down, the device internally initiates a
power-down sequence for proper shut-down. During this shut-down sequence, the NADC and MADC
dividers must not be powered down, or else a proper low power shut-down may not take place. The user
can read back the power-status flag Page 0, Register 36, D(6) and Page 0, Register 36, D(2). When both
the flags indicate power-down, the MADC divider may be powered down, followed by NADC divider.
When ADC_CLK is derived from the NDAC divider output, the NDAC must be kept powered up till the
power-down status flags for ADC do not indicate power-down. When the input to the AOSR clock divider
is derived from DAC_MOD_CLK, then MDAC must be powered up when ADC_FS is needed ( that is,
when WCLK is generated by TLV320AIC36 or AGC is enabled) and can be powered down only after the
ADC power-down flags indicate power-down status.
In general, all the root clock dividers should be powered down only after the child clock dividers have been
powered down for proper operation.
The TLV320AIC36 also has options for routing some of the internal clocks to the output pins of the device
to be used as general purpose clocks in the system. The feature is shown in Figure 5-33.
Figure 5-33. BCLK Output Options
In the mode when TLV320AIC36 is configured to drive the BCLK pin (Page 0, Register 25, D3=’1’) it can
be driven as divided value of BDIV_CLKIN. The division value can be programmed in Page 0, Register 28,
Copyright 2009–2010, Texas Instruments Incorporated
APPLICATION INFORMATION
59
Product Folder Link(s): TLV320AIC36
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| TLV320AIC36IZQER | 功能描述:接口—CODEC Low Pwr Stereo Aud Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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