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參數資料
| 型號： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁數： | 82/165頁 |
| 文件大小： | 1895K |
| 代理商： | TLV320AIC36IZQE |
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www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
The ADC must be enabled to supply biasing to the PGA. The bypass amplifiers have a fixed gain of –6 dB
for single-ended output to HP_L/HP_R and REC_L/REC_R, and 0 dB gain for differential output to
LINEOUT_L/LINEOUT_R
5.4.4
Line Input Routing
To avoid excessive internal DC offset, the line inputs should be routed to the Headphone Outputs
whenever the line inputs are activated, even if the bypass paths to the Headphone Outputs are not
needed. This can be accomplished by writing 1 to bit D7 of registers 45 and 55 in Page 2. If the line
input-to-headphone output bypass paths are not needed, they can be muted in the same registers.
5.5
Device Initialization
5.5.1
Reset
The TLV320AIC36 internal logic must be initialized to a known condition for proper device function. To
initialize the device in its default operating condition, the hardware reset pin (RESETB) must be pulled low
for at least 100 ns. For this initialization to work, the IOVDD and DVdd supplies must be powered up. It is
recommended that while the DVdd supply is being powered up, the RESETB pin be pulled low.
The device can also be reset through software by writing 1 into Page 0, Register 1 followed by writing 0
into Page 0, Register 1. After a device reset, all registers are initialized with default values as listed in the
Register Map section.
5.5.2
Device Startup Lockout Times
After the is initialized through hardware reset at power-up or software reset, the internal memories are
initialized to default values. This initialization occurs within 1 ms after pulling the RESETB signal high.
During this initialization phase, no Register read or Register write operation should be performed on ADC
or DAC coefficient buffers. Also, no block within the codec should be powered up during the initialization
phase.
5.5.3
PLL Startup
Whenever the PLL is powered up, a startup delay of approximately of 10 ms is involved after the power up
command of the PLL and before the clocks are available to the codec. This delay enables stable operation
of PLL and clock-divider logic.
5.6
ADC
5.6.1
Concept
The TLV320AIC36 includes a stereo audio ADC, which uses a delta-sigma modulator with a
programmable oversampling ratio, followed by a digital decimation filter. The ADC supports sampling rates
from 8 to 192 kHz. To provide optimal system power management, the stereo ADC can be powered up
one channel at a time, to support the case where only mono record capability is required. In addition, both
channels can be fully powered or entirely powered down. Because of the oversampling nature of the audio
ADC and the integrated digital decimation filtering, requirements for analog anti-aliasing filtering are very
relaxed. The TLV320AIC36 integrates a second-order analog anti-aliasing filter with 28-dB attenuation at 6
MHz. This filter, combined with the digital decimation filter, provides sufficient anti-aliasing filtering without
requiring additional external components.
5.6.2
Routing
As shown in Figure 5-2, the TLV320AIC36 includes eight analog inputs that can be connected to two fully
differential input amplifiers (one per ADC/PGA channel). By turning on only one set of switches per
amplifier at a time, the inputs can be effectively multiplexed to each ADC/PGA channel. By turning on
multiple sets of switches per amplifier at a time, audio sources can be mixed.
Copyright 2009–2010, Texas Instruments Incorporated
APPLICATION INFORMATION
23
Product Folder Link(s): TLV320AIC36
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相關代理商/技術參數 |
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| TLV320AIC36IZQER | 功能描述:接口—CODEC Low Pwr Stereo Aud Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320ALC23 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Evaluation Platform for the TLV320ALC23 Stereo Audio CODEC and TLV230DAC23 Stereo DAC |
| TLV320ALC31 | 制造商:BB 制造商全稱:BB 功能描述:LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY |
| TLV320DA26IRHBG4 | 功能描述:音頻數/模轉換器 IC Lo-Pwr Ster DAC w/Hdphn/Spkr Amp RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| TLV320DAC23 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO D/A CONVERTER, 8-TO 96KHZ WITH INTERGRATED HEADPHONE AMPLIFIER |
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