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參數(shù)資料
| 型號(hào)： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁數(shù)： | 124/165頁 |
| 文件大小： | 1895K |
| 代理商： | TLV320AIC36IZQE |
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PLL _ CLKIN R J.D
PLL _ CLK
P
=
MHz
20
P
CLKIN
_
PLL
kHz
512
MHz
20
P
CLKIN
_
PLL
MHz
10
www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
The PLL input supports clocks varying from 512 kHz to 20 MHz and is register programmable to enable
generation of required sampling rates with fine precision. The PLL can be turned on by writing to Page 0,
Register 5, D(7). When the PLL is enabled, the PLL output clock PLL_CLK is given by the following
equation:
(17)
Where:
R = 1, 2, 3, 4
J = 4, 5, 6,… 63, and D = 0, 1, 2… 9999
P = 1, 2, 3… 8
R, J, D, and P are register programmable.
The PLL can be programmed using Page 0, Registers 5 thru 8. The PLL can be turned on using Page 0,
Register 5, D(7). The variable P can be programmed using Page 0, Register 5, D(6:4). The default register
value for P is 2. The variable R can be programmed using Page 0, Register 5, D(3:0). The default register
value for R is 1. The variable J can be programmed using Page 0, Register 6, D(5:0). The variable D is 12
bits and is programmed into two registers. The MSB portion can be programmed using Page 0, Register
7, D(5:0), and the LSB portion is programmed using Page 0, Register 8, D(5:0). The default register value
for D is 0.
When the PLL is enabled the following conditions must be satisfied
When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN:
(18)
When the PLL is enabled and D
≠ 0, the following conditions must be satisfied for PLL_CLKIN:
(19)
The PLL can be powered up independent of the ADC and DAC blocks, and can also be used as a general
purpose PLL by routing its output to a GPIO output. After powering up the PLL, PLL_CLK is available
typically after 10 ms. The PLL output frequency is controlled by J.D and R dividers
PLL Divider
Bits
J
Page 0, Register 6, D(5:0)
D
Page 0, Register 7, D(5:0) && Page 0, Register 8, D(7:0)
R
Page 0, Register 5, D(3:0)
The D-divider value is 14-bits wide and is controlled by two registers. For proper update of the D-divider
value, Page 0, Register 7 must be programmed first followed immediately by Page 0, Register 8. Unless
the write to Page 0, Register 8 is completed, the new value of D will not take effect.
The clocks for codec and various signal processing blocks, CODEC_CLKIN can be generated from MCLK
input, BCLK input, GPIO inputs or PLL_CLK (Page 0/Register 4/D(1:0) ).
If the CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down
last.
Table 5-21 lists several example cases of typical MCLK rates and how to program the PLL to achieve a
sample rate Fs of either 44.1 or 48kHz.
Copyright 2009–2010, Texas Instruments Incorporated
APPLICATION INFORMATION
61
Product Folder Link(s): TLV320AIC36
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