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參數(shù)資料
| 型號(hào)： | TMC222-SI |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | STEPPER MOTOR CONTROLLER, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大小： | 457K |
| 代理商： | TMC222-SI |
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28
TMC222 DATASHEET (V. 1.12 / March 7, 2011)
Copyright 2004-2011 TRINAMIC Motion Control GmbH & Co. KG
6.6
Timing characteristics of the serial interface
SDA
SCL
t
f
START
t
HD;STA
t
LOW
t
r
t
HIGH
t
f
t
HD;DAT
t
SU;DAT
t
HD;STA
t
SU;STA
t
r
t
BUF
t
SU;STO
START
STOP
START
Figure 21: Definition of Timing
Parameter
Symbol
SCL Clk frequency <= 100KHz
SCL Clk frequency <= 350KHz
Unit
Min.
Max.
Min.
Max.
Low level input voltage:
Fixed input levels
VIL
-0.5
(1)
1.5
-0.5
(1)
0.3VDD
V
High level input voltage:
Fixed input levels
VIH
3.0
(2)
0.7VDD
(2)
V
Pulse width of spikes which must be
suppressed by the input filter
tSP
n/a
50
ns
Capacitance for each I/O pin
Ci
-
10
-
10
pF
Table 13: Two Wire Serial Interface - Characteristics of the SDA and SCL I/O Stages
Notes
(1): If Input voltage = < -0.3 Volts, then 20…100 Ohms resistor must be added in series
(2): Maximum VIH = VDDmax + 0.5 Volt
n/a: not applicable
Parameter
Symbol
SCL Clk frequency <= 100KHz
SCL Clk frequency <= 350KHz
Unit
Min.
Max.
Min.
Max.
SCL clock frequency
fSCL
0
100
0
350
KHz
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated.
tHD;STA
4.0
-
0.6
-
s
LOW period of the SCL clock
tLOW
4.7
-
1.3
-
s
HIGH period of the SCL clock
tHIGH
4.0
-
0.6
-
s
Set-up time for a repeated START
condition
tSU;STA
4.7
-
0.6
-
s
Data set-up time
tSU;DAT
250
-
100
-
ns
Rise time of both SDA and SCL
signals
tr
-
1000
20+0.1Cb
(1)
300
ns
Fall time of both SDA and SCL
signals
tf
-
300
20+0.1Cb
(1)
300
ns
Set-up time for STOP condition
tSU;STO
4.0
-
0.6
-
s
Bus free time between a STOP
and START condition
tBUF
4.7
-
1.3
-
s
Capacitive load for each bus line
Cb
0
400
-
400
pF
Noise margin at the LOW level for
each connected device (including
hysteresis)
VnL
0.1VDD
-
0.1VDD
-
V
Noise margin at the HIGH level for
each connected device (including
hysteresis)
VnH
0.2VDD
-
0.2VDD
-
V
Table 14: Two Wire Serial Interface - Characteristics of the SDA and SCL bus lines
Notes
(1): Cb = total capacitance of one bus line in pF.
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