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參數(shù)資料
型號(hào)： TPS65820RSHTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 8-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC56
封裝： 7 X 7 MM, GREEN, PLASTIC, QFN-56
文件頁(yè)數(shù)： 31/98頁(yè)
文件大小： 2290K
代理商： TPS65820RSHTG4
www.ti.com .............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The RESPWRON signal set to a high level is the proper signal to use as an indicator that the device has
transitioned out of the reset state. During the power-up sequence the RESPWRON pin is asserted LOW until the
RESET TIMER expires. The RESET TIME (treset = 1ms/nF × CTRSTPWON) can be programmed via a capacitor
between the TRSTPWON pin and ground.
When the RESPWRON signal is LO, all internal and external interrupts are ignored. As a result, the open-drain
output that asserts the INT pin LO during a NORMAL MODE interrupt request is disabled. The INT pin is then
asserted HI via a pullup resistor that is typically connected to VOUT. After the RESPWRON signal goes HI, the
interrupt controller is given control of the INT pin. Finally, the rising edge of the RESPWRON pin should be used
to indicate the PMIC has transitioned from the RESET STATE to the POWER GOOD CHECK STATE. At that
point, the interrupt controller asserts an interrupt if necessary.
POWER GOOD CHECK – In the power good check mode the power good comparators are enabled, providing
status on the integrated supplies output voltages. An output voltage is considered as out of regulation and
generates a fault condition if the output voltage is below 90% of the target output voltage regulation value. If a
power good fault is detected the SLEEP mode is set, if a power good fault is not detected the NORMAL mode is
set.
The individual supply power good status can be masked via an I2C register PGOODFAULT_MASK. Supplies that
have their power-good fault status masked do not generate a power good fault. However, the status bit for the
supply indicates that the output voltage is out of regulation.
The power good mask register bits default to masked upon power up.
NORMAL MODE – If a power good fault is not present at the end of the power good check mode the NORMAL
mode starts. In this mode of operation the I2C registers define the TPS65820 operation, and the host has full
control on operation modes, parameter settings, etc. The normal state operation ends if a thermal fault, system
low voltage fault ( V(SYS_IN) < VLOW_SYS ) or power good fault is detected. A thermal fault or system low voltage
fault sets the SLEEP mode operation, a power good fault sets the NO POWER operation mode. From the normal
mode the converters SM1 and SM2 can be set in the STANDBY mode, with reduced output voltages. In
NORMAL mode either an I2C register bit (SOFT_RESET register bit SOFT_RST) or a hardware input (
HOT_RESET pin set to LO) can trigger a transition to the RESET state, enabling implementation of a host reset
function. In NORMAL mode an I2C register bit (SOFT_RESET register bit SLEEP_MODE) can trigger a transition
to SLEEP mode.
SLEEP MODE – The SLEEP mode is set when a thermal fault or system low voltage fault is detected, under
NORMAL operation mode set. This operation mode is also set when a power good fault is detected during the
power good check state or via the I2C bit SLEEP_MODE. In the SLEEP mode the RESPWRON output is set to
LO, and the I2C registers keep the same contents as in the state preceding SLEEP mode, with the exception of
the following control bits, which are reset to the default power-up values:
1. LDO1,2,3,4,5 and RTC_OUT are enabled, SIM LDO is disabled: EN_LDO register set to default values
2. LDO0 disabled, all GPIOs with no control function assigned: GPIO12, GPIO3 registers set to default values
3. White LED driver is set to OFF: SM3_SET register has all bits set to LO
4. RGB drivers are set to OFF: RGB_FLASH, RGB_RED, RGB_GREEN, RGB_BLUE registers are set to
default values
5. PWM, PWM_LED drivers OFF: PWM, LED_PWM registers are set to default values
6. ADC engine reset to power up default: ADC_SET, ADC_DELAY, ADC_WAIT registers are set to default
values
In SLEEP mode, the power path and main internal blocks are still active, but the internal integrated
supply sequencing is disabled. As a result of that, during SLEEP mode ALL integrated supplies (ALL
LDO's, ALL Buck Converters) are disabled, with exception of the RTC_LDO. The RTC_LDO is ON during
sleep mode if the RTC_EN bit (register EN_LDO) is set to HI. The RTC_LDO is OFF during sleep mode if
the RTC_EN bit (register EN_LDO) is set to LO.
At the end of the SLEEP mode, the sequencer block uses the I2C control register values (which were reset to the
default power-up values) to sequence the integrated power supplies. The SLEEP mode ends when one of the
three following events happens:
1. If SLEEP was set by thermal fault: The SLEEP mode ends only when all external input supplies and battery
pack are removed and a UVLO condition is detected by the TPS65820, setting the NO POWER mode.
Copyright 2006–2008, Texas Instruments Incorporated
37
Product Folder Link(s): TPS65820
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