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參數資料
| 型號： | TPS65820RSHTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC56 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, QFN-56 |
| 文件頁數： | 66/98頁 |
| 文件大小： | 2290K |
| 代理商： | TPS65820RSHTG4 |
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8 CHANNEL
MUX
CURRENT SAMPLE
ARITHMETICLOGIC
UNIT
ANLG1
ANLG2
TJ
TS
ISET1
RTC_OUT
OUT
BAT
10 BIT SUCCESSIVE
APROXIMATION ADC
SUPPLY
REF
ACCUMULATOR
TRIGGERCONTROL
AND
SYNCHRONIZATION
START
DONE
ADCREFERENCE
ANDSUPPLY
SELECTION
BIASCONTROL
ANLG 1/
ANLG 2 BIAS
SELECTION
ADCSUPPLY
AND
REFERENCE
SELECTION
OUT
ADC
CHANNEL
SELECTION
ADCCONFIGURATION :
TRIGGER, HOLDOFF, REPEAT
MODES
DELAY ANDWAIT TIMING
ALUMODE :
SINGLE ,
AVERAGE ,
MIN,, MAX
TOI2C:
STATUS AND
CONVERSION
DATA
ADC_REF
I2C
TPS65820
A 2
4.7 F
m
ADC Conversion Cycle
www.ti.com .............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
4. Arithmetic Logic Unit (ALU): The ALU performs mathematical operations on the ADC output data as
defined by the I2C ADC_READING registers. It executes average calculations or minimum /maximum
detection. The result of the calculations is stored in an 11-bit accumulator register (1 bit allocated for
carry-over). The accumulator value is transferred to the I2C data register at the end of a conversion cycle.
A simplified block diagram for the ADC is shown in Figure 48.
Figure 48. ADC Simplified Block Diagram
A conversion cycle includes all the steps required to successfully sample the selected input signal and transfer
the converted data to the I2C, generating an interrupt request to the host ( pin : HI
→LO). The number of
individual conversions (samples) in a conversion cycle is defined by the I2C ADC_SET register bits
READ_MODE settings, and can range from a single sample to 256 samples. The conversion cycle settings for
the ALU is defined by register ADC_READING and it can be set to average, maximum value detection, minimum
value detection or no processing (ADC engine output loaded in the accumulator directly).
The conversion cycle starts with the first sampling and ends when:
The required ALU operations are performed on the final sample, and
The ALU accumulator data is transferred to the I2C ADC_READING register, and
The register bit ADC_STATUS in the ADC_READING register is set to LO.
A conversion cycle is always started by the external host when the ADC_EN bit in the ADC_SET register is
toggled from LO to HI by a I2C write operation. Resetting the ADC_EN bit to LO before the current conversion
cycle ends (INT: LO
→ HI, ADC_STATUS bit set to LO) is not recommended, as the ADC keeps its current
configuration until the current conversion cycle ends.
At the end of a conversion cycle the output data is stored at registers in the ALU block. The ADC_STATUS bit is
set to LO ( DONE ) and an interrupt is generated (INT pin : HI
→LO ) if the ADC_STATUS bit is unmasked, at the
interrupt masking registers INT_MASK. It should be noted that the minimum, maximum and average values are
ALWAYS calculated by the ALU for each conversion cycle.
Copyright 2006–2008, Texas Instruments Incorporated
69
Product Folder Link(s): TPS65820
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