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參數資料
| 型號： | TPS65820RSHTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC56 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, QFN-56 |
| 文件頁數： | 32/98頁 |
| 文件大小： | 2290K |
| 代理商： | TPS65820RSHTG4 |
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TPS65820 OPERATING MODE CONTROLS
SEQUENCING AND OPERATING MODES – I
2C REGISTERS
SLVS663B – MAY 2006 – REVISED APRIL 2008 .............................................................................................................................................................. www.ti.com
2. If SLEEP was set by a system low voltage detection, or I2C bit SLEEP_MODE, only with battery present:
Input power must be connected, setting the TPS65820 in the ENABLE mode. If no input power is inserted,
the battery discharges until the TPS65820 detects a UVLO condition and enters the NO POWER mode.
3. If sleep was set by a system low voltage detection, power good fault or SLEEP_MODE, with battery and
input power present: all external input supplies connected to AC and USB pins must be removed, and then at
least one of them reconnected to the system. The input power cycling triggers a transition from SLEEP mode
to the ENABLE mode.
PROCESSOR STANDBY STATE – This state is set using a I2C register or a GPIO configured as SM1/SM2
standby control. In standby mode operation the SM1 and SM2 voltages are set to value distinct than the normal
mode output voltage, and SM1/SM2 are set to PFM mode. The standby output voltage is defined in I2C registers
SM1_STANDBY and SM2_STANDBY.
HARDWARE RESET: A dedicated control pin, HOT_RESET, enables implementation of a hardware reset
function. The system reset pin RESPWRON is set to LO when HOT_RESET = LO for a period longer than the
internal deglitch (5 ms, typical). The RESET mode is started when the HOT_RESET pin transitions from LO to
HI, as shown in the state diagram.
SOFTWARE RESET: The external host can set the TPS65820 in RESET mode using the I2C register
SOFT_RESET, bit B0 (SOFT_RST).
SOFTWARE SLEEP: The external host can set the TPS65820 in SLEEP mode using the I2C register
SOFT_RESET, bit B6 (SLEEP_MODE).
A hardware or software reset does not affect the contents of the I2C registers.
The I2C registers that control sequencing-related functions are shown below. The HEX address for each register
is shown by the register name, together with the R or W functionality for the register bits. Shaded values indicate
default initial power-up values.
SOFT_RESET, ADDRESS=08, ALL BITS R/W, BITS B7/B6/B1/B0 APPLY TO SEQUENCING.
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
STBY MODE
SLEEP MODE
NOT USED
SM3_LF_OSc
NOT USED
nRAMLOAD
SOFT RST
Function
SET SM1 AND
SET TPS65820
NOT USED
NOT RELATED
NOT USED
RAM RESET
SOFTWARE
SM2 IN
IN SLEEP
TO
FLAG
RESET
STANDBY
MODE
SEQUENCING,
CONTROL
MODE
SEE SM3
When 0
NOT ACTIVE
NOT USED
RAM
NOT ACTIVE
DEFAULTS
SECTION
LOADED
When 1
When 1 SET
SET SLEEP
NOT USED
RAM
SET RESET
SM1 AND SM2
MODE (reset to
DEFAULTS
MODE (reset to
IN STANDBY
LO internally)
NOT LOADED
LO internally)
Some host algorithms need to identify when the power-up defaults are loaded in the RAM, in order to start
routines that initialize specific RAM registers. If that functionality is required the nRAMLOAD bit should be set to
HI by the host when entering hte NORMAL operation mode. The nRAMLOAD bit is reset to LO by the TPS65820
when the power-up defaults are loaded in the I2C registers (V(OUT)<VUVLO OR PGOOD fault detected), enabling
the host algorithm to detect that the RAM registers need to be initialized.
The integrated supplies status is available in a dedicated register, shown below. The host can select which
integrated supply outputs trigger a power good fault condition using the PGOODFAULT_MASK register.
When a non-masked power good status register bit toggles state, the sequence controller generates a transition
in the TPS65820 state machine, indicated as a PGOOD FAULT in TPS65820 state diagram.
38
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS65820
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