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參數資料
| 型號： | TS8388BCG |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| 封裝： | CBGA-72 |
| 文件頁數： | 22/46頁 |
| 文件大小： | 499K |
| 代理商： | TS8388BCG |
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TS8388BG
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6. DEFINITION OF TERMS
(BER)
Bit Error Rate
Probability to exceed a specified error threshold for a sample. An error code is a code
that differs by more than +/– 4 LSB from the correct code.
(BW)
Full power input
bandwidth
The analog input frequency at which the fundamental component in the digitally
reconstructed output has fallen by 3 dB with respect to its low frequency value
(determined by FFT analysis) for input at Full Scale.
(SINAD)
Signal to noise and
distortion ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1dB below Full Scale,
to the RMS sum of all other spectral components, including the harmonics except DC.
(SNR)
Signal to noise ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1dB below Full Scale,
to the RMS sum of all other spectral components excluding the five first harmonics.
(THD)
Total harmonic
distorsion
The ratio expressed in dBc of the RMS sum of the first five harmonic components, to
the RMS value of the measured fundamental spectral component.
(SFDR)
Spurious free
dynamic range
The ratio expressed in dB of the RMS signal amplitude, set at 1dB below Full Scale,
to the RMS value of the next highest spectral component (peak spurious spectral com-
ponent). SFDR is the key parameter for selecting a converter to be used in a frequency
domain application ( Radar systems, digital receiver, network analyzer ....). It may be
reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (i.e. always
related back to converter full scale).
(ENOB)
Effective Number Of
Bits
ENOB
+
SINAD –1.76
) 20 Log A
V 2
6.02
Where A is the actual input
amplitude and V is the full scale
range of the ADC under test
(DNL)
Differential non
linearity
The Differential Non Linearity for an output code i is the difference between the mea-
sured step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL
is the maximum value of all DNL (i). DNL error specification of less than 1 LSB guaran-
tees that there are no missing output codes and that the transfer function is monotonic.
(INL)
Integral non linearity
The Integral Non Linearity for an output code i is the difference between the measured
input voltage at which the transition occurs and the ideal value of this transition.
INL (i) is expressed in LSBs, and is the maximum value of all
|INL (i)|.
(DG)
Differential gain
The peak gain variation (in percent) at five different DC levels for an AC signal of 20%
Full Scale peak to peak amplitude. FIN = 5 MHz. (TBC)
(DP)
Differential phase
The peak Phase variation (in degrees) at five different DC levels for an AC signal of 20%
Full Scale peak to peak amplitude. FIN = 5 MHz. (TBC)
(TA)
Aperture delay
The delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero
crossing point), and the time at which (VIN,VINB) is sampled.
(JITTER)
Aperture uncertainty
The sample to sample variation in aperture delay. The voltage error due to jitter depends
on the slew rate of the signal at the sampling point.
(TS)
Settling time
Time delay to achieve 0.2 % accuracy at the converter output when a 80% Full Scale
step function is applied to the differential analog input.
(ORT)
Overvoltage recov-
ery time
Time to recover 0.2 % accuracy at the output, after a 150 % full scale step applied on
the input is reduced to midscale.
(TOD)
Digital data
Output delay
The delay from the falling edge of the differential clock inputs (CLK,CLKB) (zero cross-
ing point) to the next point of change in the differential output data (zero crossing) with
specified load.
相關PDF資料 |
PDF描述 |
|---|---|
| TS8388BCG | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| TS8388BCG | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| TS8388BMFB/T | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFSB/T | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFSB/Q | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TS8388BCGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMF | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFB/Q | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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