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參數資料
| 型號： | TS8388BCG |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| 封裝： | CBGA-72 |
| 文件頁數： | 34/46頁 |
| 文件大小： | 499K |
| 代理商： | TS8388BCG |
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TS8388BG
4/46
3. SPECIFICATIONS
3.1.
ABSOLUTE MAXIMUM RATINGS
(see note below)
Parameter
Symbol
Comments
Value
Unit
Positive supply voltage
VCC
GND to 6
V
Digital negative supply voltage
DVEE
GND to –5.7
V
Digital positive supply voltage
VPLUSD
GND–0.3 to 2.8
V
Negative supply voltage
VEE
GND to –6
V
Maximum
difference
between
negative supply voltages
DVEE to VEE
0.3
V
Analog input voltages
VIN or VINB
–1 to +1
V
Maximum difference between VIN
and VINB
VIN – VINB
–2 to +2
V
Digital input voltage
VD
GORB
–0.3 to VCC +0.3
V
Digital input voltage
VD
DRRB
VEE –0.3 to +0.9
V
Digital output voltage
Vo
VPLUSD–3 to VPLUSD –0.5
V
Clock input voltage
VCLK or VCLKB
–3 to +1.5
V
Maximum
difference
between
VCLK and VCLKB
VCLK – VCLKB
–2 to +2
V
Maximum junction temperature
Tj
+125
°C
Storage temperature
Tstg
–65 to +150
°C
Lead temperature
(soldering 10s)
Tleads
+300
°C
Notes : Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified opera-
ting conditions. Long exposure to maximum rating may affect device reliability.
The use of a thermal heat sink is mandatory (see Thermal characteristics page 16).
Note :
the ESD protections are present but not connected for Vin, Vinb, Clk and Clkb ( see section 8.1 and 8.2 )
3.2.
RECOMMENDED CONDITIONS OF USE
Parameter
Symbol
Comments
Min.
Typ.
Max.
Unit
Positive supply voltage
VCC
4.75
+5
5.25
V
Positive digital supply
voltage
VPLUSD
ECL output compatibility
+0
V
voltage
VPLUSD
LVDS output compatibility
+2.4
V
Negative supply volt-
ages
VEE, DVEE
–5.25
–5.0
–4.75
V
Differential analog input
voltage (Full Scale)
VIN, VINB
VIN –VINB
50 ohms differential or
single–ended
±125
500
mV
mVpp
Clock input power level
PCLK PCLKB
50
W single-ended clock
input
4
10
dBm
Operating temperature
range
Tc
Civil : ”C” grade
0 < Tc <+70
°C
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