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參數(shù)資料
| 型號： | TS8388BCG |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| 封裝： | CBGA-72 |
| 文件頁數(shù)： | 25/46頁 |
| 文件大小： | 499K |
| 代理商： | TS8388BCG |
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TS8388BG
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7. APPLYING THE TS8388BG
7.1.
TIMING INFORMATIONS
7.1.1.TIMING VALUE FOR TS8388BG
Timing values as defined in 3.3 are advanced data, issuing from electric simulations fitted with measurements.
Timing values are given at CBGA72 package inputs/outputs, taking into account package internal controlled impedance
traces propagation delays, gullwing pin model, and specified termination loads.
Propagation delays in 50/75 ohms impedance traces are NOT taken into account for TOD and TDR.
Apply proper derating values corresponding to termination topology.
The min/max timing values are valid over the full temperature range in the following conditions :
Note 1 : Specified Termination Load (Differential output Data and Data Ready) :
50 ohms resistor in parallel with 1 standard ECLinPS register from Motorola, (e.g : 10E452)
(Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD protections)
If addressing an output Dmux, take care if some Digital outputs do not have the same termination load and apply corre-
sponding derating value given below.
Note 2 : Output Termination Load derating values for TOD and TDR :
35 ps/pF or 50 ps per additionnal ECLinPS load.
Note 3 :Propagation time delay derating values have also to be applied for TOD and TDR :
6 ps/mm (155 ps/inch) for TSEV8388B Evaluation Board.
Apply proper time delay derating value if a different dielectric layer is used.
7.1.2.PROPAGATION TIME CONSIDERATIONS
TOD and TDR Timing values are given from pin to pin and DO NOT include the additionnal propagation times between
device pins and input/output termination loads. For the TSEV8388B Evaluation Board, the propagation time delay is
6ps/mm (155ps/inch) corresponding to 3.4 (@10GHz) dielectric constant of the RO4003 used for the Board.
If a different dielectric layer is used (for instance Teflon), please use appropriate propagation time values.
TD does NOT depend on propagation times because it is a differential data.
(TD is the time difference between Data Ready output delay and digital Data output delay)
TD is also the most straightforward data to measure, again because it is differential :
TD can be measured directly onto termination loads, with matched Oscilloscopes probes.
7.1.3.TOD – TDR VARIATION OVER TEMPERATURE
Values for TOD and TDR track each other over temperature ( 1 percent variation for TOD – TDR per 100 degrees Cel-
sius temperature variation ). Therefore TOD – TDR variation over temperature is negligible. Moreover, the internal
(onchip) and package skews between each Data TODs and TDR effect can be considered as negligible.
Consequently, minimum difference between TOD and TDR are never more than 100 ps. The same is true for the TOD
and TDR maximum values. In other terms :
If TOD is at 1150 ps, TDR will not be at 1620 ps ( maximum time delay for TDR ).
If TOD is at 1660 ps, TDR will not be at 1110 ps ( minimum time delay for TDR ) However, external TOD – TDR values
may be dictated by total digital datas skews between every TODs (each digital data) and TDR :
MCM Board , bonding wires and output lines lengths differences, and output termination impedance mismatches.
The external (on board) skew effect has NOT been taken into account for the specification of the minimum and maxi-
mum values for TOD–TDR.
7.1.4.PRINCIPLE OF OPERATION
The Analog input is sampled on the rising edge of external clock input (CLK,CLKB) after TA (aperture delay) of typically
250 ps .
The digitized data is available after 4 clock periods latency (pipeline delay (TPD)), on clock rising edge, after 1360 ps
typical propagation delay TOD.
The Data Ready differential output signal frequency (DR,DRB) is half the external clock frequency, that is it switches at
the same rate as the digital outputs.
The Data Ready output signal (DR,DRB) switches on external clock falling edge after a propagation delay TDR of typi-
cally 1320 ps.
A Master Asynchronous Reset input command DRRB ( ECL compatible single–ended input) is available for initializing
the differential Data Ready output signal ( DR,DRB ) .This feature is mandatory in certain applications using interleaved
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| TS8388BCG | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| TS8388BCG | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TS8388BCGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMF | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFB/Q | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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