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參數(shù)資料
型號(hào): TS8388BCG
元件分類(lèi): ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
封裝: CBGA-72
文件頁(yè)數(shù): 30/46頁(yè)
文件大小: 499K
代理商: TS8388BCG
TS8388BG
36/46
The TS8388BG output buffers are designed for driving 75 ohms (default) or 50 ohms properly terminated impedance
lines or coaxial cables.
An 11 mA bias current flowing alternately into one of the 75 ohms resistors when switching ensures a 0.825 V voltage
drop across the resistor (unterminated outputs).
The VPLUSD positive supply voltage allows the adjustment of the output common mode level from –1.2V (VPLUSD=0V
for ECL output compatibility) to +1.2V (VPLUSD=2.4V for LVDS output compatibility).
Therefore,the single ended output voltages vary approximately from –0.8V to –1.625V ( outputs unterminated ), around
–1.2V common mode voltage.
Three possible line driving and back–termination scenarios are proposed (assuming VPLUSD=0V) :
1 ) 75 Ohms impedance transmission lines, 75 ohms differentialy terminated (Fig. 3) :
Each output voltage varies between –1V and –1.42V (respectively +1.4V and +1V), leading to +/– 0.41V =0.825 V in
differential, around –1.21 V (respectively +1.21V) common mode for VPLUSD=0V (respectively 2.4V).
2 ) 50 ohms impedance transmission lines, 50 ohms differentialy termination (Fig. 4) :
Each output voltage varies between –1.02V and –1.35V (respectively +1.38V and +1.05V), leading to +/– 0.33V=660
mV in differential, around –1.18V (respectively +1.21V) common mode for VPLUSD=0V (respevtively 2.4V).
3 ) 75 ohms impedance open transmission lines (Fig. 5) :
Each output voltage varies between –1.6 V and –0.8 V (respectively +0.8V and +1.6V), which are true ECL levels, lead-
ing to +/– 0.8V=1.6V in differential, around –1.2V (respectively +1.2V) common mode for VPLUSD=0V (respectively
2.4V).
Therefore, it is possible to drive directly high input impedance storing registers, without terminating the 75 ohms trans-
mission lines.
In time domain, that means that the incident wave will reflect at the 75 ohms transmission line output and travel back to
the generator ( i.e. the 75 ohms data output buffer ). As the buffer output impedance is 75 ohms, no back reflection will
occur.
Note : This is no longer true if a 50 ohms transmission line is used, as the latter is not matching the buffer 75 ohms output
impedance.
Each differential output termination length must be kept identical .
It is recommended to decouple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode
perturbation in case of slight mismatch in the differential output line lengths.
Too large mismatches ( keep < a few mm ) in the differential line lengths will lead to switching currents flowing into the
decoupling capacitor leading to switching ground noise.
The differential output voltage levels ( 75 or 50 ohms termination ) are not ECL standard voltage levels, however it is
possible to drive standard logic ECL circuitry like the ECLinPS logic line from MOTOROLA.
At sampling rates exceeding 1GSPS, it may be difficult to trigger the HP16500 or any other Acquisition System with
digital outputs.
It becomes necessary to regenerate digital data and Data Ready by means of external amplifiers, in order to be able to
test the TS8388BG at its optimum performance conditions.
相關(guān)PDF資料
PDF描述
TS8388BCG 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
TS8388BCG 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
TS8388BMFB/T 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
TS8388BMFSB/T 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TS8388BCGL 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays
TS8388BCGL (+LID) 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays
TS8388BMF 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays
TS8388BMFB/Q 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays
TS8388BMFS 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays
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