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參數資料
| 型號： | TS8388BCG |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| 封裝： | CBGA-72 |
| 文件頁數： | 27/46頁 |
| 文件大小： | 499K |
| 代理商： | TS8388BCG |
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TS8388BG
33/46
Differential inputs voltage span
–125
125
[mV]
–250 mV
250 mV
VIN
500mV
Full Scale
analog input
t
VINB
(VIN,VINB)=+/– 250 mV = 500 mV diff
0 Volt
Differential versus single ended analog input operation
The TS8388BG can operate at full speed in either differential or single ended configuration.
This is explained by the fact the ADC uses a high input impedance differential preamplifier stage, (preceding the Sample
and hold stage), which has been designed in order to be entered either in differential mode or single-ended mode.
Thus the differential analog input preamplifier will fully reject the local ground noise ( and any capacitively and induc-
tively coupled noise) as common mode effects.
In typical single-ended configuration, enter on the (VIN) input pin, with the inverted phase input pin (VINB) grounded
through the 50 ohms termination resistor.
In single-ended input configuration, the in–phase input amplitude is 0.5 Volt peak to peak,centered on 0V. (or –2 dBm
into 50 ohms.)
The inverted phase input is at ground potential through the 50 ohms termination resistor.
However, dynamic performances can be somewhat improved by entering either analog or clock inputs in differential
mode.
Typical Single ended analog input configuration
–250
250
[mV]
500 mV
Full Scale
analog input
t
VIN = ± 250 mV 500 mVpp diff
VINB
VIN
VINB = 0V
VIN or VINB
VIN or VINB pad (pins L3, L4)
50
(package)
50
reverse termination
1M
3 pF
7.4.
CLOCK INPUTS (CLK) (CLKB)
The TS8388BG can be clocked at full speed without noticeable performance degradation in either differential or single
ended configuration.
This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has been designed
in order to be entered either in differential or single-ended mode.
7.4.1.SINGLE ENDED CLOCK INPUT (GROUND COMMON MODE)
Although the clock inputs were intended to be driven differentially with nominal –0.8V / –1.8V ECL levels, the TS8388BG
clock buffer can manage a single-ended sinewave clock signal centered around 0 Volt. This is the most convenient clock
input configuration as it does not require the use of a power splitter.
No performance deterioration ( e.g. : due to timing jitter) is observed in this particular single-ended configuration up to
1.2GSPS Nyquist conditions ( Fin = 600 MHz ).
This is true as long as the inverted phase clock input pin is 50 ohms terminated very close to one of the neighbouring
shield ground pin, which constitutes the local Ground reference for the inphase clock input.
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PDF描述 |
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| TS8388BCG | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| TS8388BCG | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| TS8388BMFB/T | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFSB/T | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFSB/Q | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TS8388BCGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMF | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFB/Q | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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