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參數(shù)資料
| 型號： | TS8388BCG |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| 封裝： | CBGA-72 |
| 文件頁數(shù)： | 28/46頁 |
| 文件大小： | 499K |
| 代理商： | TS8388BCG |
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TS8388BG
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Thus the TS8388BG differential clock input buffer will fully reject the local ground noise ( and any capacitively and induc-
tively coupled noise) as common mode effects.
Moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance.
The typical inphase clock input amplitude is 1 Volt peak to peak, centered on 0 Volt (ground) common mode.
This corresponds to a typical clock input power level of 4 dBm into the 50 ohms termination resistor.
Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors.
The inverted phase clock input is grounded through the 50 ohms termination resistor.
Single ended Clock input (Ground common mode)
VCLK common mode = 0 Volt
VCLKB=0 Volt
4 dBm typical clock input power level
(into 50 ohms termination resistor)
[V]
t
VCLK
VCLKB = ( 0 V )
–0.5V
+0.5V
CLK or CLKB
50
(on package)
50
reverse termination
1M
0.4 pF
CLK or CLKB pad (pins C1, D1)
Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock input power level.
7.4.2.DIFFERENTIAL ECL CLOCK INPUT
The clock inputs can be driven differentially with nominal –0.8V / –1.8V ECL levels.
In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, followed by a power splitter
(hybrid junction) in order to obtain 180 degrees out of phase sinewave signals. Biasing tees can be used for offseting the
common mode voltage to ECL levels.
Note : As the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the
signals to be 180 degrees out of phase especially at fast clock rates in the GSPS range.
Differential Clock inputs (ECL Levels)
–0.8V
[mV]
t
–1.8V
VCLKB
VCLK
Common mode = –1.3 V
CLK or CLKB
50
(on package)
50
reverse termination
1M
0.4 pF
–2V
CLK or CLKB pad (pins C1, D1)
7.4.3.SINGLE ENDED ECL CLOCK INPUT
In single-ended configuration enter on CLK ( resp. CLKB ) pin , with the inverted phase Clock input pin CLKB (respec-
tively CLK) connected to –1.3V through the 50 ohms termination resistor.
The inphase input amplitude is 1 Volt peak to peak, centered on –1.3 Volt common mode.
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PDF描述 |
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| TS8388BCG | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| TS8388BCG | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| TS8388BMFB/T | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFSB/T | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFSB/Q | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TS8388BCGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMF | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFB/Q | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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