
5.4.7
DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
5.4.8
DAC Playback on Line Out (10 k-
load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.0
5.5 Audio ADC and Analog Inputs
5.5.1
MICBIAS and Microphone Preamplifier
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
SLAS550A – APRIL 2009 – REVISED JUNE 2009
www.ti.com
HVDD = 3.3 V
DOSR = 32, Processing Block = PRB_P17 (Interpolation Filter C)
Power consumption = 27.05 mW
Table 5-13. PRB_P17 Alternative Processing Blocks, 27.05 mW
Processing Block
Filter
Estimated Power Change (mW)
PRB_P18
C
5.28
PRB_P19
C
1.98
V,
HVDD = 3.0 V
DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B)
Power consumption = 12.85 mW
The TSC2117 includes a microphone bias circuit which can source up to 4 mA of current, and is
programmable to a 2-V, 2.5-V, or AVDD level. The level can be controlled by writing to page 1/register 46,
bits D1–D0. This functionality is shown in
Table 5-14.
Table 5-14. MICBIAS Settings
D1
D0
FUNCTIONALITY
0
MICBIAS output is powered down.
0
1
MICBIAS output is powered to 2 V.
1
0
MICBIAS output is powered to 2.5 V.
1
MICBIAS output is powered to AVDD.
During normal operation, MICBIAS can be set to 2.5 V for better performance. However, depending on the
model of microphone that is selected, optimal performance might be obtained at another setting, so the
performance at a given setting should be verified.
The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current
consumption occurs when MICBIAS is set at AVDD.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog anti-aliasing filtering are very relaxed. The TSC2117 integrates a second-order
analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimal
filter, provides sufficient anti-aliasing filtering without requiring any external components.
The MIC PGA supports analog gain control from from 0 dB to 59.5 dB in steps of 0.5 dB. These gain
levels can be controlled by writing to page 1/register 47, bits D6–D0. The PGA gain changes are
implemented with internal soft-stepping. This soft-stepping ensures that volume-control changes occur
smoothly with no audible artifacts. On reset, the MIC PGA gain defaults to a mute condition, with soft
stepping enabled. The ADC soft-stepping control can be enabled or disabled by writing to
page 0/register 81, bits D1–D0. ADC soft-stepping timing is provided by the internal oscillator and internal
divider logic block.
APPLICATION INFORMATION
28