
Programmable
Divider
Page3/Register2,BitsD4–D3
ADCSARClock
ADCSAR
ConversionClock
Interval Timers
Internal
Oscillator
Poweredonif
RC_CLKIs
Selected
8
RC_CLK
RC_CLK/8
SignalUsedforSAR ADCLogic,
Finite-State-Machine(FSM)Panel
VoltageStabilization Time,
Pre-Charge Time,Sense Time
ToSAR ADC
Debounce TimeforPen-Touch
Removal.
Generation
UsedforProgrammable
Interval Timersforthe12-bitSAR.
AlsoUsedforDebounce Timefor
HeadsetDetectionLogicandfor
ofVariousInterrupts.
Programmable
Divider
Page3/Register17,BitsD6–D0
Page3/Register17,BitD7
MCLK
1
0
Programmable
Divider
Page3/Register16,BitsD6–D0
Page3/Register16,BitD7
0
1
B0213-02
To Avoid AsynchronousClockDomain
Issues, AlwaysSelecttheSameValuefor:
Page3/Register16,BitD7
Page3/Register17,BitD7
5.7.1.3 Touch Detect/Data Available – GPIO1 or GPIO2 Programmed as PINTDAV Signal
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
SLAS550A – APRIL 2009 – REVISED JUNE 2009
www.ti.com
Figure 5-40. SAR ADC and Interval Timer Clock Selection
Regardless of the conversion clock speed, the internal clock runs nominally at 8.2 MHz. The conversion
time of the TSC2117 depends on several functions. While the conversion clock speed plays an important
role in the time it takes for a conversion to complete, a certain number of internal clock cycles are needed
for proper sampling of the signal. Moreover, additional times, such as the panel voltage stabilization time,
can add significantly to the time it takes to perform a conversion. Conversion time can vary, depending on
the mode in which the TSC2117 is used. Throughout this data sheet, internal and conversion clock cycles
are used to describe the times that many functions take to execute. Considering the total system design,
these times must be taken into account by the user.
The ADC uses either the internal MCLK signal or the internal oscillator for the SAR conversions.
The interrupt pins (GPIO1 or GPIO2) can be programmed for three functions by writing to
page 0/register 51, bits D5–D2 (GPIO1) or page 0/register 52, bits D5–D2 (GPIO2) the value of 1100. In
this case, these pins function as the PINTDAV signal. The default setting of PINDAV is for pen interrupt
(PENIRQ). However, it could be used for a data-available interrupt (DATA_AVA), or it can be set up for
signaling when either a pen interrupt occurs or the ADC data is available (PENIRQ and DATA_AVA). To
APPLICATION INFORMATION
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