
5.5.3
Delta-Sigma ADC
5.5.4
ADC Decimation Filtering and Signal Processing
5.5.4.1 ADC Processing Blocks
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
SLAS550A – APRIL 2009 – REVISED JUNE 2009
www.ti.com
The analog-to-digital converter has a delta-sigma modulator with an oversampling ratio (AOSR) up to 128.
The ADC can support a maximum output rate of 192 kHz.
ADC power up is controlled by writing to page 0/register 81, bit D7. An ADC power-up condition can be
verified by reading page 0/register 36, bit D6.
The TSC2117 ADC channel includes built-in digital decimation filters to process the oversampled data
from the delta-sigma modulator to generate digital data at the Nyquist sampling rate with high dynamic
range. The decimation filter can be chosen from three different types, depending on the required
frequency response, group delay, and sampling rate.
The TSC2117 offers a range of processing blocks which implement various signal processing capabilities
along with decimation filtering. These processing blocks give users the choice of how much and what type
of signal processing they may use and which decimation filter is applied.
The choices among these processing blocks allow the system designer to balance power conservation
and signal-processing flexibility. Less signal-processing capability reduces the power consumed by the
device.
Table 5-16 gives an overview of the available processing blocks of the ADC channel and their
properties. The Resource Class (RC) column gives an approximate indication of power consumption.
The signal processing blocks available are:
First-order IIR
Scalable number of biquad filters
Variable-tap FIR filter
AGC
The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group
delay in combination with various signal-processing effects such as audio effects and frequency shaping.
The available first-order IIR, biquad, and FIR filters have fully user-programmable coefficients.
Table 5-16. ADC Processing Blocks
Processing
Decimation
1st Order
Number
Required
Resource
Channel
FIR
Blocks
Filter
IIR Available
BiQuads
AOSR Value
Class
PRB_R4
Mono
A
Yes
0
No
128, 64
3
PRB_R5
Mono
A
Yes
5
No
128, 64
4
PRB_R6
Mono
A
Yes
0
25-tap
128, 64
4
PRB_R10
Mono
B
Yes
0
No
64
2
PRB_R11
Mono
B
Yes
3
No
64
2
PRB_R12
Mono
B
Yes
0
20-tap
64
2
PRB_R16
Mono
C
Yes
0
No
32
2
PRB_R17
Mono
C
Yes
5
No
32
2
PRB_R18
Mono
C
Yes
0
25-tap
32
2
APPLICATION INFORMATION
32