
5.9.1.1 Right-Justified Mode
BCLK
WCLK
SDIN/SDOUT
n-1 n-2
1
0
n-1 n-2
1
0
LSB
MSB
LeftChannel
RightChannel
n-3
2
n-3
LSB
MSB
1/fs
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
www.ti.com
SLAS550A – APRIL 2009 – REVISED JUNE 2009
configuring page 0/register 27, D(5:4). In addition, the word clock and bit clock can be independently
configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The
word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a
square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and
DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in page 0/register 30 (see
Figure 5-58). The number of bit-clock pulses in a frame may need adjustment to
accommodate various word-lengths as well as to support the case when multiple TSC2117s may share
the same audio bus.
The TSC2117 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in page
0/register 28.
The TSC2117 also has the feature of inverting the polarity of the bit-clock used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the mode
of audio interface chosen. This can be configured via page 0/register 29, D(3).
The TSC2117 further includes programmability (page 0/register 27, D0) to 3-state the SDOUT line during
all bit clocks when valid data is not being sent. By combining this capability with the ability to program at
what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished,
enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data bus is
powered down while configured in master mode, the pins associated with the interface are put into a
3-state output condition.
By default when the word-clocks and bit-clocks are generated by the TSC2117, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power.
However, it also supports a feature when both the word clocks and bit-clocks can be active even when the
codec in the device is powered down. This is useful when using the TDM mode with multiple codecs on
the same bus, or when word-clock or bit-clocks are used in the system as general-purpose clocks.
The audio interface of the TSC2117 can be put into right-justified mode by programming page 0/register
27, D(7:6) = 10. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit
clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the
rising edge of the bit clock preceding the rising edge of the word clock.
Figure 5-61. Timing Diagram for Right-Justified Mode
For right-justified mode, the number of bit-clocks per frame should be greater than or equal to twice the
programmed word-length of the data.
APPLICATION INFORMATION
93