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參數資料
| 型號： | Z684 |
| 英文描述： | FUSE 3A/125V SUB-MINIATURE PICO |
| 中文描述： | 控制器雜項-數據表參考 |
| 文件頁數： | 1/13頁 |
| 文件大小： | 129K |
| 代理商： | Z684 |
1
OKI SEMICONDUCTOR
Z684 PCI Bus Controller
0.5
μ
m Technology Mega Macrocell
DESCRIPTION
The PCI Bus Controller Mega Macrocell is a featured element in OKI’s 0.5
tomer Structured Array (CSA) families. Designers can significantly reduce design and simulation effort
by using OKI's Z684 on PCI bus interface projects. The Z684 is fully compliant with the PCI Bus Revision
2.0 specification.
μ
m Sea of Gates (SOG) and Cus-
OKI's Z684 provides a PCI interface, data FIFO and control, and a configuration block in a highly inte-
grated module for system design interfaces that implement the PCI bus protocol. The Z684 connects
between an external PCI bus and a peripheral device’s internal 486-like bus. Both buses are 32 bits wide
and operate at clock frequencies of up to 33 MHz. Two 4x36-bit write FIFOs enhance system performance.
The cell also supports address and data parity generation and error reporting. PCI-compliant I/ O buffers
are available to connect the Z684 to a PCI bus, and are added when the design is implemented in an SOG
array or CSA. By using the Z684, the users may speed up the design cycle and accelerate market entry for
the end product.
FEATURES
Highly integrated interfaces between
customer's application specific design
module and PCI bus
Compliant with PCI Bus Revision 2.0
specification
Internal, i486-like 32-bit address and data bus
interface, with byte-select-enable control
Two 4x36-bit address, data and byte-enable
write FIFOs
32-bit PCI address and data bus interface
with byte-select-enable control
3-V operation
Supported ASIC Families
Family Name
Family Type
MSM10R0000
Sea of Gates
MSM13R0000
Sea of Gates
MSM98R000
Customer Structured Array
Built-in internal 64-byte PCI configuration
registers, which can be accessed both from
PCI and module buses
Built-in memory and I/ O address decoding
Burst write mode operation on both PCI and
module interfaces
Full support for PCI master and slave
functions
Full address parity generation, data parity
generation and error checking and correction
(ECC)
Synchronous operation at up to 33 MHz for
both the PCI and module interfaces
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