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參數資料
| 型號： | Z684 |
| 英文描述： | FUSE 3A/125V SUB-MINIATURE PICO |
| 中文描述： | 控制器雜項-數據表參考 |
| 文件頁數： | 10/13頁 |
| 文件大小： | 129K |
| 代理商： | Z684 |
I
Z684 PCI Bus Controller
I
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10
OKI SEMICONDUCTOR
Customer Application Module may have its own external I/ Os, which do not interface with the Z684 and
which may have their own memory or I/ O space. In this document, the term
cifically to the Customer Application Module.
module
by itself refers spe-
Module/Z684 Interface Bus (“Module Bus”)
This is an i486-like bus which interfaces between the customer’s module and the Z684. This protocol was
chosen because more designers are familiar with the x86 protocol than any other bus protocol; in addition,
the i486 bus protocol is easy to understand. On the module bus, all signals are unidirectional signals, and
are either inputs or outputs of the Z684. In this manual, the term
ule/ Z684 interface bus.
module bus
specifically refers to the mod-
Internal PCI Bus
All Z684 interface signals are unidirectional signals. For each bidirectional PCI signal, the Z684 has three
corresponding unidirectional signals: one input, one output and one enable signal.
The input signal starts with an “I” prefix
The output signal starts with an “O” prefix
The enable signal starts with an “E” prefix
Low-assertion output signals end with “B” suffix.
For example, the PCI target ready signal TRDY# has three corresponding Z684 signals: ITRDYB for input,
OTRDYB for output and ETRDYB for enable. When the enable signal is asserted (the enable signal is
asserted LOW for most PCI signals), the output is valid and the input signal is in a “don't care” state.
When the enable signal is deasserted, the input is valid and the output is 3-stated.
To avoid confusion with formal bidirectional PCI signals, all unidirectional Z684 PCI signals are called
“internal” PCI signals. These signals form an internal PCI bus interface between the Z684 and PCI I/ O
buffers.
PCI I/O Buffers
These are I/ O buffers to convert the internal unidirectional PCI signals into formal PCI bus signals. The
buffers also provide the signal drive strengths defined by PCI electrical specifications. The following table
lists the available PCI I/ O buffers. These buffers must be placed in the design by the designer.
PCI I/O Buffer Macrocells
Family
Cell Name
Equivalent SSO Current(mA)
GND
VDD
MSM13R/98R
OTPCILH
24
12
ODPCILH
24
—
BTPCILH
24
12
OTPCILL
12
12
BTPCILL
12
12
MSM10R
OTPCI
24
24
BTPCI
24
24
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