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參數(shù)資料
| 型號(hào)： | Z684 |
| 英文描述： | FUSE 3A/125V SUB-MINIATURE PICO |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大小： | 129K |
| 代理商： | Z684 |
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Z684 PCI Bus Controller
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6
OKI SEMICONDUCTOR
PCI Interface Signals
The PCI interface signals are signals between the Z684 and the PCI bus. The PCI interface signals are uni-
directional versions of normal PCI signals.
Input signals (driven from the PCI bus to the Z684) start with an “I” prefix.
Output signals (driven from the Z684 to the module) start with an “O” prefix.
Enable signals start with an “E” prefix.
All low assertion signals end with a “B” suffix.
PCI Interface Signals
Signal
Type
Assertion
Description
PCLK
Input
–
PCI Clock.
transactions. The current version of the Z684 requires that both MCLK and PCLK are
connected to the same clock driver.
The PCLK signal synchronizes all bus cycles and control signals for Z684-PCI
RSTB
Input
LOW
PCI Reset.
When asserted to LOW, RSTB resets all the Z684-PCI interface control logic.
REQB
Output
LOW
PCI Bus Request
REQB LOW, signaling a PCI bus access request to the PCI bus arbiter.
. Whenever a direct transaction to the PCI bus is pending, the Z684 asserts
GNTB
Input
LOW
PCI Bus Grant
is available for access.
. The PCI bus arbiter asserts GNTB LOW to signal to the Z684 that the PCI bus
IDSEL
Input
HIGH
IDSEL PCI Configuration Access
or write cycle is pending.
. The IDSEL input indicates that a configuration register read
IDEVSELB
Input
LOW
Device Select.
selected for access. The IDEVSELB pin is the input signal for the PCI DEVSEL# pin.
The PCI target asserts IDEVSELB low to signal to the Z684 that it has been
IFRAMEB
Input
LOW
Frame Input.
and duration of a transaction cycle. The initiator deasserts IFRAMEB in the clock cycle before
the last data phase of the transaction cycle. The IFRAMEB pin is the input signal for the PCI
FRAME# pin.
When driven low by an initiator, the IFRAMEB signal indicates the beginning
IIRDYB
Input
LOW
Initiator Data Ready.
the initiator's ability to complete the current data phase. This signal is the input signal for the
PCI IRDY# pin.
When the initiator drives the IIRDYB signal low, this signal indicates
ILOCKB
Input
LOW
ILOCKB Input.
transactions to complete. The ILOCKB signal is the input pin for the PCI LOCK# signal.The
ILOCKB signal is used only when system memory is supported. This pin is not supported in
the current Z684 version and must be tied inactive (HIGH).
This signal indicates that an atomic operation may require multiple
ISTOPB
Input
LOW
Stop or Retry Input
initiator to stop the current transaction. The ISTOPB signal is the input pin for the PCI STOP#
signal.
. The ISTOPB signal indicates that the current target is requesting the
ITRDYB
Input
LOW
ITRDYB Input
phase of the transaction. The ITRDYB signal is the input signal for the PCI TRDY# pin.
. This signal indicates that the target device is able to complete the current data
IPAR
Input
–
Parity
The IPAR signal is the input pin for the PCI PAR signal.
. This signal provides even parity across the PCI address/data and byte enable buses.
IPERRB
Input
LOW
Parity Error
errors during all PCI transactions except special cycles. The IPERRB signal is the input pin for
the PCI PERR# signal.
. This is the parity error reporting signal. The IPERRB signal reports data parity
ISERRB
Input
LOW
System Error
data parity errors. The ISERRB signal is the input pin for the PCI SERR# signal.
. This is the system error signal. This input reports address and special cycle
IAD[31:0]
Input
–
AD Address and Data Bus
. These are the PCI multiplexed address and data bus inputs.
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