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參數(shù)資料
型號: Z684
英文描述: FUSE 3A/125V SUB-MINIATURE PICO
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 4/13頁
文件大?。?/td> 129K
代理商: Z684
I
Z684 PCI Bus Controller
I
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4
OKI SEMICONDUCTOR
SIGNAL DESCRIPTIONS
The Z684 signals can be classified into two main groups:
Module Interface Signals
PCI Interface Signals
All Z684 signals are unidirectional and unbuffered.
Module Interface Signals
Module Interface Signals interface the Z684 with the customer’s application module. Module Interface
Signals are either Z684 inputs or Z684 outputs.
Input signals (driven from the module to the Z684) start with an “M” prefix
Output signals (driven from the Z684 to the module) start with a “P” prefix
Low assertion-signals end with “B” suffix
The Module Interface Signals are derived from 486-like external bus signals and have the same function
as equivalent i486 signals.
Module Interface Signals
Signal
Type
Assertion
Description
MCLK
Input
Module Clock.
transactions. The current version of the Z684 requires that both MCLK and PCLK are connected to the same
clock driver.
The MCLK signal synchronizes all bus cycles and control signals for module-Z684
MRESET
Input
HIGH
Module Reset.
control logic.
When asserted HIGH, MRESET resets all components related with Z684-PCI interface
MADSB
Input
LOW
Module Address Strobe
bus is valid. This signal also indicates the beginning of a bus cycle.
. When asserted LOW, MADSB indicates that the address on the MA[31:0] address
MBLASTB
Input
LOW
Module Burst Last
data phase.
. When asserted LOW, MBLASTB indicates that the transaction cycle has entered the final
MRDYB
Input
LOW
Module Data Ready
PD[31:0].
. This signal indicates that the module has received valid data from the Z684 data bus,
MM_IOB
Input
Module Memory or I/O Select
access is selected.
. When asserted HIGH, memory access is selected. When asserted LOW, I/O
MD_CB
Input
Module Data or Code Select
LOW, the bus performs a code access cycle.
. When asserted HIGH, the bus performs a data access cycle. When asserted
MWR_RDB
Input
Module Write or Read.
performs a write cycle. When asserted LOW, the bus performs a read cycle.
This signal defines a write or read bus cycle. When asserted HIGH, the bus
MLOCKB
Input
LOW
Module Lock Cycle Request
This signal is not supported in the current version of the Z684 and must be tied inactive (HIGH).
. When asserted LOW, the module performs a locked transaction.
MHLDA
Input
HIGH
Module Bus Hold Acknowledge
module is available to receive a transaction from the Z684. This signal is equivalent to the i486 bus signal
HLDA.
. When asserted HIGH, this signal indicates that the customer application
MCS0
Input
HIGH
Module Chip Select 0
asserted HIGH, the Z684’s internal configuration registers are selected.
. This signal indicates an access cycle to the internal configuration registers. When
MCS1
Input
HIGH
Module Chip Select 1
external PCI memory or I/O, or PCI configuration register space.
. This signal indicates a PCI bus transaction. When asserted HIGH, this signal selects
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